AMD EFR-DI-25GEMAC-RLL

Overview

EF-R-DI-25GEMAC-RLL from Xilinx is a low-latency 25G Ethernet Media Access Controller (MAC) with integrated Physical Coding Sublayer (PCS), compliant with IEEE 802.3 Clause 49 and 25G Ethernet Consortium specifications. It operates at 25.78125 Gb/s line rate, delivers 46.08 ns end-to-end latency on 64-bit AXI4-Stream interface at 390.625 MHz, and targets Zynq UltraScale+ MPSoC, Virtex UltraScale+, and Kintex UltraScale+ FPGAs for data center NIC and switch fabric applications.

For engineers reviewing the EFR-DI-25GEMAC-RLL datasheet, pinout, applications, or equivalent options, this IP core enables deterministic 25G MAC+PCS integration with runtime 10G/25G switching, RS-FEC (Clause 108), IEEE 1588 timestamping, and AXI4-Lite control - critical for TSN-aware infrastructure and high-throughput server interconnects.

Technical Context

This subsystem implements a full 64B/66B encode/decode pipeline with asynchronous gearbox interfacing to Xilinx GTY transceivers. It supports both 10.3125 Gb/s (Clause 49) and 25.78125 Gb/s serial rates, with configurable pause processing per IEEE 802.3 Annex 31D and optional clause 74 FEC (2112,2080).

The low-latency variant bypasses internal FIFOs to achieve sub-50 ns latency, uses dedicated rx_clk_out and tx_clk_out domains synchronized to SerDes reference clocks, and exposes status/control via AXI4-Lite registers - enabling real-time diagnostics, statistics gathering, and dynamic configuration of preamble, inter-frame gap, and preemption (802.1CM) in 10G mode only.

Key Specifications

Pinout & Package

This is an FPGA intellectual property (IP) core - not a physical component. It has no package, die, or pinout. Interface signals are defined in RTL and instantiated within Vivado Design Suite as synthesizable Verilog modules. Signal mapping follows Xilinx GTY transceiver I/O conventions and AXI4-Stream protocol semantics.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 25G Ethernet MAC+PCS applications.

Compared with EFR-DI-25GEMAC-RLL, EFR-DI-25GEMAC-PROJ offers richer diagnostics but identical 25G latency, while Intel's hard IP trades runtime switching and soft configurability for lower power and deterministic placement - making EFR-DI-25GEMAC-RLL optimal for latency-sensitive, multi-rate FPGA-based infrastructure.

Availability

EF-R-DI-25GEMAC-RLL is available at Aetrix Electronics and suitable for data center switch fabric, high-performance server NIC, 5G fronthaul, industrial TSN gateway, and AI cluster interconnect applications requiring stable component supply and long-term IP license continuity.

Supply support for EFR-DI-25GEMAC-RLL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now part of AMD) is a semiconductor company specializing in adaptive computing solutions, including FPGA, SoC, and ACAP technologies for high-performance, low-latency system design.

EF-R-DI-25GEMAC-RLL belongs to Xilinx's LogiCORE IP portfolio for high-speed networking - engineered specifically for ultra-low-latency 25G Ethernet MAC+PCS integration in UltraScale+ and Versal platforms used in cloud infrastructure and real-time edge systems.

FAQ

What is the exact latency of EFR-DI-25GEMAC-RLL at 25G line rate?

The EFR-DI-25GEMAC-RLL achieves 46.08 ns end-to-end latency when operating at 25.78125 Gb/s with a 64-bit AXI4-Stream interface clocked at 390.625 MHz. This measurement includes TX MAC, PCS encoding, and RX PCS decoding paths under low-latency FIFO-bypass mode - verified in Xilinx PG210 v2.4 Table 2-1. The EFR-DI-25GEMAC-RLL latency is fixed for this configuration and does not vary with packet size or traffic load.

Does EFR-DI-25GEMAC-RLL support IEEE 1588 timestamping in both 10G and 25G modes?

Yes, EFR-DI-25GEMAC-RLL supports IEEE 1588 v2 1-step and 2-step hardware timestamping in both 10G and 25G operational modes. Timestamp insertion occurs at the MAC layer on transmit and extraction at the MAC layer on receive, with sub-nanosecond resolution enabled by dedicated clock domain alignment. The EFR-DI-25GEMAC-RLL implements full PTP message parsing and correction field handling per IEEE 1588-2008.

Can EFR-DI-25GEMAC-RLL be used without purchasing a separate license?

No - EFR-DI-25GEMAC-RLL requires a fee-based license key (xxv_eth_mac_pcs) for full functionality in simulation and hardware. While base 10G/25G BASE-R PCS/PMA is included with Vivado Design Suite at no extra cost, the EFR-DI-25GEMAC-RLL MAC+PCS variant is licensed separately. License enforcement occurs during Vivado Synthesis and Implementation; generation halts if the EFR-DI-25GEMAC-RLL license key is missing or invalid.

Which FPGA families support EFR-DI-25GEMAC-RLL?

EF-R-DI-25GEMAC-RLL is validated for Zynq UltraScale+ MPSoC, Virtex UltraScale+, Kintex UltraScale+, Virtex UltraScale, and Kintex UltraScale FPGAs. It relies on GTY transceivers and UltraScale+ architecture timing resources - it is not supported on 7-series, Spartan, or Artix devices. The EFR-DI-25GEMAC-RLL instantiation requires Vivado 2017.4 or later and is delivered as encrypted RTL with device-specific constraints.

Does EFR-DI-25GEMAC-RLL include RS-FEC (Clause 108) support?

Yes, EFR-DI-25GEMAC-RLL includes optional IEEE 802.3by Clause 108 25G Reed-Solomon Forward Error Correction as a configurable feature. When enabled, the EFR-DI-25GEMAC-RLL integrates full RS(544,514) encoder/decoder logic inline with the PCS layer, correcting burst errors up to 16 symbols and improving link BER to <1e-15 - critical for 25G KR/KR4 backplane and CR4 copper applications.