AMD EFR-DI-25GEMAC-SITE

Overview

EF-R-DI-25GEMAC-SITE from Xilinx is a licensable IP core implementing a 25 Gb/s Ethernet Media Access Controller (MAC) with integrated Physical Coding Sublayer (PCS), compliant with IEEE 802.3by and 25G Ethernet Consortium specifications. It delivers 64-bit AXI4-Stream user interface, 46.08 ns latency at 390.625 MHz, supports RS-FEC (Clause 108), IEEE 1588 timestamping, and runtime 10G/25G switching - deployed in Zynq UltraScale+ MPSoC and Virtex/Kintex UltraScale+ FPGAs for data center NICs and switch uplinks.

For engineers reviewing the EFR-DI-25GEMAC-SITE datasheet, pinout, applications, or equivalent options, this page provides verified functional scope, latency benchmarks, AXI4-Stream timing behavior, transceiver interface mapping, and validated alternative IP licensing options - all specific to the SITE license variant of the MAC+PCS subsystem.

Technical Context

The EFR-DI-25GEMAC-SITE implements a full 25G Ethernet MAC+PCS stack operating at 25.78125 Gb/s line rate using Xilinx GTY transceivers with Asynchronous Gearbox enabled. It integrates 64B/66B encoding/decoding, scrambler/descrambler, pause processing per IEEE 802.3 Annex 31D, and optional RS-FEC per Clause 108.

It exposes dual-clock-domain AXI4-Stream interfaces: tx_clk_out at 390.625 MHz drives transmit signals (tx_axis_tdata[63:0], tx_axis_tvalid, tx_axis_tlast), while rx_clk_out at same frequency clocks receive path; control/status uses optional AXI4-Lite. Latency is fixed at 46.08 ns for 64-bit 25G operation.

Key Specifications

Availability

EFR-DI-25GEMAC-SITE is available at Aetrix Electronics and suitable for high-bandwidth data center networking, FPGA-based network interface cards (NICs), and Top-of-Rack (TOR) switch uplink designs requiring stable component supply, long-term IP license continuity, and Vivado-integrated verification support.

Supply support for EFR-DI-25GEMAC-SITE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now AMD Adaptive SoC Business Unit) is a semiconductor company specializing in programmable logic devices, FPGA-based system-on-chip solutions, and high-performance IP cores for networking, AI acceleration, and embedded vision.

The EFR-DI-25GEMAC-SITE belongs to Xilinx's LogiCORE IP portfolio targeting high-speed wired connectivity. It was designed specifically to accelerate 25G Ethernet adoption in FPGA-based infrastructure equipment where low-latency, standards-compliant MAC+PCS integration is required.

FAQ

What is the EFR-DI-25GEMAC-SITE and how is it licensed?

EFR-DI-25GEMAC-SITE is a site-licensed Xilinx LogiCORE IP core for 25G Ethernet MAC+PCS functionality. Unlike project-based licenses, it permits unlimited use across all designs and projects within a single physical location. The core requires Vivado Design Suite and valid license keys (e.g., xxv_eth_mac_pcs) for synthesis and implementation - no additional hardware purchase is needed.

Does EFR-DI-25GEMAC-SITE support both 10G and 25G operation?

Yes, EFR-DI-25GEMAC-SITE supports runtime-switchable 10G/25G operation. When configured for 25G, it runs at 25.78125 Gb/s with 390.625 MHz AXI4-Stream clock and 46.08 ns latency; in 10G mode, it operates at 10.3125 Gb/s with 156.25 MHz clock and 115.2 ns latency. Switching occurs dynamically via control registers without FPGA reconfiguration.

What transceiver families does EFR-DI-25GEMAC-SITE target?

EFR-DI-25GEMAC-SITE is validated for Xilinx GTY transceivers in Virtex UltraScale+, Kintex UltraScale+, and Zynq UltraScale+ MPSoC devices. It relies on GTY's native 25.78125 Gb/s capability and requires Asynchronous Gearbox mode for clock domain crossing between GTY and the MAC/PCS logic - no support for older GTH or GTZ transceivers.

Is RS-FEC (Clause 108) included by default in EFR-DI-25GEMAC-SITE?

No, RS-FEC per IEEE 802.3 Clause 108 is an optional, fee-based feature for EFR-DI-25GEMAC-SITE. It requires the separate license key ieee802d3_25g_rs_fec_full and must be explicitly enabled during IP customization in Vivado. Without this license, the core operates with baseline BASE-R PCS only.

Can EFR-DI-25GEMAC-SITE be used without an AXI4-Lite control interface?

Yes, EFR-DI-25GEMAC-SITE supports configuration without AXI4-Lite. In minimal mode, static parameters (e.g., RS-FEC enable, 1588 mode) are set at generation time via Vivado GUI or TCL, and status monitoring is limited to dedicated output signals (e.g., tx_stat, rx_stat). AXI4-Lite is optional but required for dynamic runtime control and full statistics register access.