AMD EFR-DI-25G-TSN-802-1-CM-PROJ

Overview

EF-R-DI-25G-TSN-802-1-CM-PROJ from Xilinx is a licensable IP subsystem implementing IEEE 802.1CM-compliant Time-Sensitive Networking frame preemption for 10 Gigabit Ethernet MAC+PCS, operating at 10.3125 Gb/s with 64-bit AXI4-Stream interface, low latency (115.2 ns), and integrated pause processing - deployed in data center NICs and industrial TSN switches requiring deterministic traffic scheduling.

For engineers reviewing the EFR-DI-25G-TSN-802-1-CM-PROJ datasheet, pinout, applications, or equivalent options, this page delivers verified functional scope, latency benchmarks, AXI4-Stream timing behavior, TSN preemption implementation details, and Vivado-integrated licensing requirements - all specific to the 10G-only TSN-enabled variant.

Technical Context

This subsystem implements the IEEE 802.1CM (802.3br/802.1bu) frame preemption feature exclusively within the 10G MAC+PCS variant, inserting express frames into low-priority frame transmission using fragment-based interruption and reassembly. It operates only at 10.3125 Gb/s with Clause 49 BASE-R encoding and requires external GTY transceiver integration via rx_serdes_data_p0/n0 and tx_serdes_data_p0/n0 interfaces.

The IP includes AXI4-Lite control/status registers for preemption enable/disable, fragment counter monitoring, and error reporting, while user data flows through a 64-bit AXI4-Stream interface clocked at 156.25 MHz. No runtime 10G/25G switching capability is present - unlike the broader EFR-DI-25G family, this part is fixed at 10G with TSN preemption enabled.

Key Specifications

Pinout & Package

This is a synthesizable RTL IP core, not a physical component. It has no package or pinout. Integration occurs via Verilog/VHDL top-level wrapper with defined logical ports mapped to FPGA fabric resources and transceiver GTY primitives.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar TSN Ethernet MAC applications.

Compared with EF-DI-25GEMAC-PROJ, EFR-DI-25G-TSN-802-1-CM-PROJ trades runtime flexibility and minimal latency for certified 802.1CM preemption compliance - essential for IEC 61784-2 and IEEE 802.1Qbv deployments - while EF-DI-25G-TSN-802-1-CM-SITE offers identical technical capability under broader licensing terms.

Availability

EFR-DI-25G-TSN-802-1-CM-PROJ is available at Aetrix Electronics and suitable for industrial TSN switch design, automotive zonal gateway development, and test & measurement equipment requiring stable component supply with long-term IP license continuity.

Supply support for EFR-DI-25G-TSN-802-1-CM-PROJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now AMD Adaptive SoC Business Unit) designs programmable logic and adaptive compute platforms for high-performance embedded and data center applications.

This IP belongs to the 10G/25G High Speed Ethernet Subsystem product line, engineered specifically for deterministic Ethernet in TSN-constrained environments - targeting IEEE 802.1CM preemption, low-latency forwarding, and Vivado-integrated verification.

FAQ

What is the primary function of EFR-DI-25G-TSN-802-1-CM-PROJ?

EF-R-DI-25G-TSN-802-1-CM-PROJ is a Xilinx Vivado IP core that implements IEEE 802.1CM-compliant frame preemption exclusively for 10 Gigabit Ethernet MAC+PCS operation. It enables express traffic to interrupt low-priority frame transmission and guarantees correct reassembly - a mandatory capability for time-critical industrial TSN networks. The EFR-DI-25G-TSN-802-1-CM-PROJ does not support 25G operation or runtime switching.

Does EFR-DI-25G-TSN-802-1-CM-PROJ support 25G Ethernet operation?

No. EFR-DI-25G-TSN-802-1-CM-PROJ is strictly a 10G-only variant with fixed 10.3125 Gb/s operation per IEEE 802.3 Clause 49. Although its part number contains "25G", this reflects membership in the broader 10G/25G IP family; the TSN preemption feature was only implemented and validated for 10G MAC+PCS configurations. The EFR-DI-25G-TSN-802-1-CM-PROJ cannot operate at 25.78125 Gb/s.

What clock frequency is required for EFR-DI-25G-TSN-802-1-CM-PROJ?

EF-R-DI-25G-TSN-802-1-CM-PROJ requires a 156.25 MHz clock for its 64-bit AXI4-Stream interface when operating at 10.3125 Gb/s. This clock drives both transmit and receive datapaths and must be phase-aligned with the GTY transceiver's rx_clk_out and tx_clk_out domains. The EFR-DI-25G-TSN-802-1-CM-PROJ does not support 32-bit AXI4-Stream or alternate clock frequencies.

Is AXI4-Lite interface mandatory for EFR-DI-25G-TSN-802-1-CM-PROJ?

No. The AXI4-Lite control/status interface is optional in EFR-DI-25G-TSN-802-1-CM-PROJ. When disabled, preemption remains active by default, but runtime monitoring of fragment counters, error flags, and preemption enable state is unavailable. Enabling AXI4-Lite provides register access to IEEE 802.1CM-specific status bits - critical for certification testing and debug visibility in safety-critical deployments.

What license key is required to use EFR-DI-25G-TSN-802-1-CM-PROJ in Vivado?

The EFR-DI-25G-TSN-802-1-CM-PROJ requires the xxv_tsn_802d1cm license key, enforced during Vivado Synthesis and write_bitstream. This is a fee-based license distinct from the free 10G/25G BASE-R PCS/PMA IP. The EFR-DI-25G-TSN-802-1-CM-PROJ also inherits the xxv_eth_mac_pcs key for underlying MAC+PCS functionality, but xxv_tsn_802d1cm is mandatory to unlock preemption logic.