AMD EFR-DI-25G-TSN-802-1-CM-SITE

Overview

EF-R-DI-25G-TSN-802-1-CM-SITE from Xilinx is a licensable IP subsystem implementing IEEE 802.1CM-compliant Time-Sensitive Networking frame preemption for 10 Gb/s Ethernet MAC+PCS operation on UltraScale+ FPGAs. It delivers 36.8 ns latency at 312.5 MHz, supports 64-bit AXI4-Stream user interface and optional AXI4-Lite control, and integrates with GTY transceivers for 10.3125 Gb/s serial I/O - deployed in data center NICs requiring deterministic low-latency traffic shaping.

For engineers reviewing the EFR-DI-25G-TSN-802-1-CM-SITE datasheet, pinout, applications, or equivalent options, this page provides verified functional scope, latency metrics, TSN preemption implementation details, AXI interface timing, and licensing context specific to the SITE license model.

Technical Context

The EFR-DI-25G-TSN-802-1-CM-SITE implements the IEEE 802.1CM (802.3br/802.1bu) frame preemption feature exclusively within the 10G MAC+PCS variant - not supported in 25G mode or PCS-only configurations. It operates at 312.5 MHz with 32-bit or 64-bit AXI4-Stream interface, and requires integration with Xilinx GTY transceivers for physical layer connectivity.

This IP core embeds preemption logic that enables high-priority express frames to interrupt transmission of lower-priority frames mid-packet, using the 802.1CM-defined preemption point insertion and fragment reassembly protocol. It relies on external configuration via AXI4-Lite registers and generates status signals including tx_preempt_active and rx_preempt_status.

Key Specifications

Availability

EFR-DI-25G-TSN-802-1-CM-SITE is available at Aetrix Electronics and suitable for data center NICs, industrial TSN switches, and FPGA-based network accelerators requiring stable component supply, long-term IP license continuity, and certified 802.1CM preemption functionality.

Supply support for EFR-DI-25G-TSN-802-1-CM-SITE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now part of AMD) is a semiconductor company specializing in adaptive computing solutions, including FPGA, SoC, and ACAP platforms for high-performance networking, AI acceleration, and embedded systems.

The EFR-DI-25G-TSN-802-1-CM-SITE belongs to the 10G/25G High Speed Ethernet Subsystem IP family, designed specifically to enable standards-compliant, low-latency, time-sensitive Ethernet implementations in Xilinx UltraScale+ MPSoC and Virtex UltraScale+ FPGAs.

FAQ

Does EFR-DI-25G-TSN-802-1-CM-SITE support 25G Ethernet with IEEE 802.1CM preemption?

No. The EFR-DI-25G-TSN-802-1-CM-SITE implements IEEE 802.1CM frame preemption exclusively for 10 Gb/s operation (10.3125 Gb/s, Clause 49). Per Xilinx PG210 v2.4, 25G preemption is not supported - the TSN feature is limited to the 10G MAC+PCS variant. EFR-DI-25G-TSN-802-1-CM-SITE does not enable preemption at 25.78125 Gb/s.

What is the minimum latency of EFR-DI-25G-TSN-802-1-CM-SITE and under what conditions is it achieved?

The measured latency of EFR-DI-25G-TSN-802-1-CM-SITE is 36.8 ns when configured as the 32-bit 10G MAC+PCS variant operating at 312.5 MHz. This value excludes transceiver PHY latency and assumes low-latency buffer bypass mode with no FIFO insertion. Latency increases in 64-bit mode (115.2 ns) and is not defined for 25G operation since preemption is disabled there.

Which Xilinx device families are supported by EFR-DI-25G-TSN-802-1-CM-SITE?

EFR-DI-25G-TSN-802-1-CM-SITE is validated for Zynq UltraScale+ MPSoC, Virtex UltraScale+, Kintex UltraScale+, Virtex UltraScale, and Kintex UltraScale FPGAs. It requires GTY transceivers and is incompatible with 7-series devices or non-UltraScale architecture parts. Device support is enforced by Vivado IP catalog constraints.

Is AXI4-Lite interface mandatory for configuring EFR-DI-25G-TSN-802-1-CM-SITE preemption features?

No. AXI4-Lite is optional but required to access IEEE 802.1CM-specific registers such as PREEMPT_CTRL, PREEMPT_STATUS, and fragment counters. Without AXI4-Lite, preemption cannot be enabled or monitored - the EFR-DI-25G-TSN-802-1-CM-SITE core defaults to standard non-preemptive 10G MAC operation even when licensed.

What license key is required to implement EFR-DI-25G-TSN-802-1-CM-SITE in Vivado?

The EFR-DI-25G-TSN-802-1-CM-SITE requires the xxv_tsn_802d1cm license key. This key must be installed alongside xxv_eth_mac_pcs (for MAC+PCS base functionality) and x_eth_mac (legacy 10GEMAC compatibility). License enforcement occurs during Vivado Synthesis and Implementation - bitstream generation fails without all three keys.