AMD EFR-DI-CANFD-XA-SITE

Overview

EF R-DI-CANFD-XA-SITE from Xilinx is a LogiCORE IP soft core implementing the ISO 11898-1:2015 CAN FD protocol for FPGA-based automotive and industrial control systems. It supports both classical CAN and CAN FD frames up to 64 bytes, flexible data rates exceeding 4 Mb/s, and operates via AXI4-Lite host interface with external PHY connectivity. It is deployed in Zynq-7000 SoCs and UltraScale+ FPGAs for body control units and sensor networks.

For engineers reviewing the EFR-DI-CANFD-XA-SITE datasheet, pinout, applications, or equivalent options, this page delivers verified architectural details, register-level timing control, mailbox/FIFO buffer configuration, ISO-compliant bit timing registers, and mode-selectable operation (Snoop, Loopback, Sleep) - all essential for FPGA integration and CAN FD protocol stack development.

Technical Context

The EFR-DI-CANFD-XA-SITE implements a dual-layer architecture: an AXI4-Lite–facing Object Layer (in AXI clock domain) handles register access, TX/RX buffer management, and message scheduling; and a CAN clock–domain Transfer Layer performs bit stuffing, CRC calculation (including stuff-bit count for FD frames), bit rate switching, arbitration, ACK handling, and error detection per ISO 11898-1:2015.

It requires external PHY connection for bus signaling and supports configurable TX/RX buffer depths, 32-deep sequential RX FIFO with 32 ID filter-mask pairs, and timestamping for transmitted/received messages. Core initialization mandates software reset via SRR register, and mode transitions (Normal/Snoop/Loopback/Sleep) are controlled through the Mode Select Register (MSR) with strict mutual exclusion enforced.

Key Specifications

Availability

EF R-DI-CANFD-XA-SITE is available at Aetrix Electronics and suitable for automotive body control units, industrial sensor networks, and embedded test equipment requiring stable component supply and long-term FPGA IP licensing continuity.

Supply support for EFR-DI-CANFD-XA-SITE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now part of AMD) is a semiconductor company specializing in programmable logic devices, FPGA architectures, and high-performance IP cores for adaptive computing solutions.

The EFR-DI-CANFD-XA-SITE belongs to Xilinx's LogiCORE IP portfolio and was designed specifically to accelerate ISO-compliant CAN FD implementation in automotive and industrial FPGA systems - eliminating custom RTL development while ensuring protocol conformance and timing accuracy.

FAQ

What is the functional role of EFR-DI-CANFD-XA-SITE in a Zynq-7000 design?

The EFR-DI-CANFD-XA-SITE serves as a synthesizable soft IP core that implements the full CAN FD protocol stack inside the programmable logic of Zynq-7000 SoCs. It interfaces with ARM Cortex-A9 processors via AXI4-Lite and connects to external CAN transceivers through dedicated can_phy_tx/can_phy_rx signals. EFR-DI-CANFD-XA-SITE handles bit-level arbitration, CRC generation, bit rate switching, and message buffering - offloading protocol complexity from software and enabling deterministic real-time communication.

Does EFR-DI-CANFD-XA-SITE require a Bosch license for deployment?

Yes - a valid Bosch CAN FD protocol license is mandatory before selling any end-product containing the EFR-DI-CANFD-XA-SITE. This requirement is explicitly stated in the PG223 documentation and enforced during Vivado synthesis and implementation checkpoints. The license covers use of the proprietary CAN FD protocol specification and applies regardless of whether ISO or non-ISO frame formats are selected in the core configuration.

How does EFR-DI-CANFD-XA-SITE handle error management and bus-off recovery?

EF R-DI-CANFD-XA-SITE implements full ISO 11898-1 error counters (TEC/REC), automatic bus-off detection, and configurable recovery modes. The Mode Select Register (MSR) provides dedicated bits - ABR (Auto Bus-off Recovery) and SBR (Start Bus-off Recovery) - to initiate and control recovery sequences. Error status is reported via ESR and ISR registers, and error logging is separated for nominal and fast data-rate phases to support diagnostic traceability in safety-critical systems.

Can EFR-DI-CANFD-XA-SITE operate without an external PHY?

No - EFR-DI-CANFD-XA-SITE is a digital logic core only and requires an external CAN FD transceiver (PHY) for physical layer signaling. The core provides can_phy_tx and can_phy_rx signals for direct connection to the PHY; it does not include driver circuitry, termination, or voltage-level translation. This separation ensures compliance with ISO 11898-2 electrical standards and allows selection of PHYs optimized for specific EMC, voltage, or fault-tolerance requirements.

What clock domains does EFR-DI-CANFD-XA-SITE use, and how are they synchronized?

EF R-DI-CANFD-XA-SITE uses two independent clock domains: the AXI4-Lite interface operates in the s_axi_aclk domain (host processor clock), while the CAN protocol engine runs in the can_clk domain (derived from external oscillator). Data exchange between layers - such as TX buffer requests or RX message writes - is handled by CDC synchronizers embedded in the core. This dual-domain architecture prevents metastability and ensures reliable cross-clock transfers without user-implemented handshaking logic.