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AMD EFR-DI-CANFD-XA-WW
- Part No.:
- EFR-DI-CANFD-XA-WW
- Manufacturer:
- AMD
- Category:
- Software, Services
- Package:
- Datasheet:
-
EFR-DI-CANFD-XA-WW.pdf
- Description:
- LOGICORE, CANFD FOR AUTOMOTIVE D
- Quantity:
- Payment:
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Inventory:1,518
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Product details
Overview
EF R-DI-CANFD-XA-WW from Xilinx is a LogiCORE IP soft core implementing the ISO 11898-1:2015 CAN FD protocol for FPGA-based automotive and industrial control systems. It supports both classical CAN and CAN FD frames up to 64 bytes, flexible data rates exceeding 4 Mb/s, and operates via AXI4-Lite host interface with external PHY connectivity - deployed in body control units, sensor networks, and Zynq-7000 SoC designs.
For engineers reviewing the EFR-DI-CANFD-XA-WW datasheet, pinout, applications, or equivalent options, this page delivers verified functional scope, register-mapped I/O behavior, ISO-compliant timing configuration, and FPGA resource integration guidance - all specific to the EFR-DI-CANFD-XA-WW implementation in UltraScale+, Zynq-7000, and 7 Series devices.
Technical Context
The EFR-DI-CANFD-XA-WW implements a dual-layer architecture: an AXI4-Lite–facing Object Layer (in s_axi_aclk domain) handles register access, TX/RX buffer management, and timestamping; and a CAN clock–domain Transfer Layer performs bit stuffing, CRC calculation (including stuff-bit count for FD), bit rate switching, arbitration, ACK handling, and error signaling per ISO 11898-1:2015.
It supports configurable operating modes - Normal, Snoop (bus monitoring), Sleep (with wake-up interrupt), and internal Loopback - each with distinct error counter behavior and bus participation rules. The core requires external PHY connection and mandates a Bosch CAN FD protocol license for commercial deployment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Protocol Compliance | ISO 11898-1:2015 - ensures interoperability with automotive-grade CAN FD networks and certified ECUs. |
| Frame Support | Classical CAN (up to 8 bytes) and CAN FD (up to 64 bytes) - enables legacy compatibility and high-throughput diagnostics/data logging. |
| Data Rate | Flexible data rate > 4 Mb/s - allows burst-mode payload transmission without increasing nominal arbitration rate. |
| Host Interface | AXI4-Lite - provides standardized, non-burst register-mapped access compatible with MicroBlaze and ARM Cortex-A9 processors. |
| Buffer Architecture | 32-deep RX FIFO + 32 ID Filter-Mask pairs, or up to 48 RX mailboxes - supports scalable message filtering and deterministic latency in real-time control loops. |
| Timing Control | Separate Arbitration Phase (BRPR/BTR) and Data Phase (DP_BRPR/DP_BTR) registers - enables independent tuning of nominal and fast bit timing for robust multi-node timing alignment. |
| Error Handling | Dedicated TX/RX error logging, bus-off recovery (manual/auto), and Protocol Exception Event (PEE) detection - critical for ASIL-B–aligned fault reporting in safety-critical systems. |
Pinout & Package
EF R-DI-CANFD-XA-WW is a soft IP core with no physical package or fixed pinout. Its interface consists entirely of synthesizable RTL signals mapped to FPGA logic resources. Implementation requires user-defined top-level port connections per target device.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| s_axi_aclk | AXI4-Lite Clock Input | Synchronizes register reads/writes and internal AXI handshake - must be stable during configuration and runtime. |
| can_clk | CAN Protocol Clock Input | Drives bit timing logic (arbitration & data phase); oscillator tolerance must meet ISO 11898-1 specification. |
| can_phy_tx / can_phy_rx | PHY Interface Signals | Direct connection to external CAN transceiver (e.g., TJA1042); no internal PHY - board-level signal integrity design required. |
| ip2bus_intrevent | Interrupt Output | Active-high level-sensitive interrupt indicating TX ready, RX full, bus-off, or error events - requires CPU-side edge detection or polling. |
Key Features
| Feature | Design Value |
|---|---|
| ISO CAN FD Frame Format Selection | Configurable at synthesis time to match either ISO 11898-1:2015 or Bosch non-ISO format - ensures compliance with regional OEM requirements. |
| Transmitter Delay Compensation | Up to three data bit delay correction - mitigates timing skew between TX path and PHY output in high-speed FD operation. |
| TX Message Cancellation | Runtime abort of pending transmissions via TCR register - prevents stale commands from reaching the bus during mode transitions or fault recovery. |
| Timestamping | 16-bit timestamp counter on TX/RX messages - enables precise event correlation and jitter analysis in distributed control systems. |
| Snoop Mode | Non-intrusive bus monitoring with disabled ACK and cleared error counters - supports diagnostic sniffing without affecting network arbitration. |
Applications
| Automotive Body Control Unit | Industrial Sensor Network |
|---|---|
|
Use Scenario: Centralized control of door locks, lighting, HVAC, and window actuators across multiple ECUs. IC Role / Device Role / Timing Role: CAN FD protocol engine managing high-bandwidth firmware updates and synchronized actuator commands via Zynq-7000 SoC. Use Value: 64-byte FD frames reduce update cycle time by >3× vs classical CAN, while ISO 11898-1:2015 compliance ensures OEM validation acceptance. |
Use Scenario: Real-time aggregation of temperature, pressure, and vibration data from distributed field sensors in factory automation. IC Role / Device Role / Timing Role: FPGA-based CAN FD endpoint interfacing with analog front-ends and Ethernet gateways using AXI4-Lite host control. Use Value: Flexible data rate >4 Mb/s enables sub-100 µs sensor sampling intervals without bus congestion, supporting closed-loop PID response. |
| Automotive Test Equipment | Instrument Cluster Communication |
|
Use Scenario: Hardware-in-the-loop (HIL) test bench simulating ECU behavior and injecting fault conditions on live CAN FD buses. IC Role / Device Role / Timing Role: Dual-mode CAN FD core operating in Snoop + Loopback to monitor traffic and inject synthetic frames without bus arbitration impact. Use Value: Independent TX/RX buffer management and timestamping allow precise stimulus-response latency measurement down to ±1 bit time. |
Use Scenario: Digital instrument cluster rendering speed, RPM, and ADAS alerts using data from powertrain and ADAS ECUs. IC Role / Device Role / Timing Role: CAN FD receiver integrated into UltraScale+ FPGA, filtering and forwarding prioritized messages to display controller via AXI interconnect. Use Value: 32 ID Filter-Mask pairs enable selective reception of 32+ message IDs with zero CPU overhead, ensuring deterministic UI update timing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar CAN FD protocol engine applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Xilinx LogiCORE IP CAN v2.0 | Supports classical CAN only (max 8-byte frames, ≤1 Mb/s); no CAN FD, no data-phase timing registers, no 64-byte buffers. | Suitable for legacy vehicle subsystems or cost-sensitive industrial nodes where FD bandwidth is unnecessary. | Select only if ISO 11898-1:2015 FD compliance and >4 Mb/s data bursts are not required. |
| NXP SJA1105Q Ethernet TSN Switch with CAN FD Offload | Hardware-accelerated CAN FD controller embedded in multi-port TSN switch; fixed silicon implementation, not programmable RTL. | Used in gateway applications requiring simultaneous CAN FD, Ethernet AVB/TSN, and VLAN routing - not for standalone FPGA protocol offload. | Choose when integrating CAN FD with time-synchronized Ethernet; avoid when FPGA logic reuse, custom filtering, or AXI host integration is needed. |
Compared with Xilinx LogiCORE IP CAN v2.0, EFR-DI-CANFD-XA-WW adds ISO-compliant FD frame handling, 64-byte payloads, and dual-phase bit timing - essential for modern automotive diagnostics. Against NXP SJA1105Q, it trades fixed-function integration for FPGA flexibility, enabling custom pre-processing, security wrappers, and co-processing with other IP.
Availability
EF R-DI-CANFD-XA-WW is available at Aetrix Electronics and suitable for automotive body control units, industrial sensor networks, and instrument cluster communication requiring stable component supply and long-term FPGA IP licensing support.
Supply support for EFR-DI-CANFD-XA-WW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Xilinx (now part of AMD) is a leader in adaptive computing, delivering FPGA, SoC, and ACAP platforms for high-performance, low-latency system design.
EF R-DI-CANFD-XA-WW belongs to the LogiCORE IP portfolio - designed specifically to accelerate ISO-compliant CAN FD integration into Xilinx FPGAs and SoCs for automotive and industrial real-time networks.
FAQ
What is the licensing requirement for deploying EFR-DI-CANFD-XA-WW in production hardware?
A valid Bosch CAN FD protocol license is mandatory before selling any device containing the EFR-DI-CANFD-XA-WW core. Xilinx enforces license checks during Vivado synthesis and implementation; generation halts without a verified license key. The license covers both automotive and non-automotive use cases under separate agreement terms.
Does EFR-DI-CANFD-XA-WW include an integrated CAN transceiver (PHY)?
No, EFR-DI-CANFD-XA-WW is a digital logic core only and requires an external CAN FD–compliant transceiver (e.g., NXP TJA1042T, ST TDFM1200) connected via can_phy_tx and can_phy_rx signals. Board-level design must ensure proper termination, common-mode filtering, and ESD protection per ISO 11898-2.
How does EFR-DI-CANFD-XA-WW handle bus-off recovery?
EF R-DI-CANFD-XA-WW supports both manual and automatic bus-off recovery. Setting the ABR bit in the Mode Select Register triggers auto-recovery; setting SBR initiates manual recovery. Recovery completes after detecting 128 occurrences of 11 consecutive recessive bits, returning the core to Error Active state - fully documented in the PG223 register map.
Can EFR-DI-CANFD-XA-WW operate without a MicroBlaze or ARM processor?
Yes. EFR-DI-CANFD-XA-WW functions in stand-alone mode using direct AXI4-Lite register access from custom HDL logic - no processor is required. Example Verilog test benches demonstrate bare-metal initialization, TX scheduling, and RX polling without software drivers.
What FPGA families are supported by EFR-DI-CANFD-XA-WW?
EF R-DI-CANFD-XA-WW is validated for UltraScale+, UltraScale, Zynq-7000 All Programmable SoC, and 7 Series devices. Resource utilization varies by target family and configuration; exact LUT/FF/BRAM counts are published on Xilinx's Performance and Resource Utilization web page referenced in PG223.
EFR-DI-CANFD-XA-WW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- AMD
- Series:
- LogiCORE™
- Packaging:
- Electronic Delivery
- Product Status:
- Active
- Type:
- License
- Applications:
- -
- Edition:
- -
- License Length:
- 1 Year Renewal
- License - User Details:
- Worldwide
- Operating System:
- -
- For Use With/Related Products:
- Xilinx
- Media Delivery Type:
- Electronically Delivered
EFR-DI-CANFD-XA-WW FAQ
1.How can I place an order for EFR-DI-CANFD-XA-WW through Aetrix?
Please submit a Request for Quotation (RFQ) for EFR-DI-CANFD-XA-WW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for EFR-DI-CANFD-XA-WW reliable?
The price and inventory of EFR-DI-CANFD-XA-WW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for EFR-DI-CANFD-XA-WW is usually 5 days.
3.What payment methods are accepted for EFR-DI-CANFD-XA-WW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for EFR-DI-CANFD-XA-WW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for EFR-DI-CANFD-XA-WW?
EFR-DI-CANFD-XA-WW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your EFR-DI-CANFD-XA-WW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for EFR-DI-CANFD-XA-WW?
For technical support, including EFR-DI-CANFD-XA-WW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your EFR-DI-CANFD-XA-WW requirements.
6.How does Aetrix verify that EFR-DI-CANFD-XA-WW is sourced from the original manufacturer or authorized distributors?
All EFR-DI-CANFD-XA-WW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that EFR-DI-CANFD-XA-WW meets industry standards.
7.What is the process for return or replacement of EFR-DI-CANFD-XA-WW?
All EFR-DI-CANFD-XA-WW units undergo pre-shipment inspection (PSI). If there is an issue with EFR-DI-CANFD-XA-WW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The EFR-DI-CANFD-XA-WW part is unused and in its original packaging.
Return procedure for EFR-DI-CANFD-XA-WW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
EFR-DI-CANFD-XA-WW Tags
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