AMD EFR-DI-CANFD-XC-SITE

Overview

EF R-DI-CANFD-XC-SITE from Xilinx is a LogiCORE IP soft core implementing the ISO 11898-1:2015 CAN FD protocol for FPGA-based automotive and industrial control systems. It supports dual-rate operation (nominal up to 1 Mbps, data phase >4 Mbps), 64-byte payload frames, AXI4-Lite host interface, and integrated TX/RX mailbox and FIFO buffers - deployed in Zynq-7000 SoCs and UltraScale+ FPGAs for body control units and sensor networks.

For engineers reviewing the EFR-DI-CANFD-XC-SITE datasheet, pinout, applications, or equivalent options, this page delivers verified architecture details, register-mapped I/O signals, buffer configuration options, timing register layout, and mode-select behavior - all aligned with PG223 v1.0 specification and Vivado IP catalog integration requirements.

Technical Context

The EFR-DI-CANFD-XC-SITE implements a layered architecture: an AXI4-Lite–facing Object Layer (register module, TX/RX buffer managers) operating in the s_axi_aclk domain, and a CAN clock–synchronized Transfer Layer handling bit timing, arbitration, CRC calculation, bit stuffing/de-stuffing, and bit rate switching. CDC synchronizers bridge the two clock domains.

It supports both ISO and non-ISO CAN FD frame formats, configurable TX cancellation and RX filtering (32 ID mask pairs), timestamping for TX/RX messages, and operational modes including Snoop (bus monitoring), Sleep (wake-up interrupt), Loopback, and Normal - all controlled via dedicated bits in the Mode Select Register (MSR) and Status Register (SR).

Key Specifications

Pinout & Package

EF R-DI-CANFD-XC-SITE is a synthesizable RTL IP core with no physical package. It is instantiated in Xilinx FPGAs (UltraScale+, UltraScale, Zynq-7000, 7 Series) and interfaces via logical ports defined in PG223. Core I/O signals include AXI4-Lite host interface (s_axi_*), can_clk, ip2bus_intrevent, can_phy_tx, and can_phy_rx.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CAN FD controller applications.

Compared with EFR-DI-CANFD-XC-SITE, the SJA1105Q offers integrated Ethernet switching but lacks FPGA flexibility and AXI4-Lite configurability, while the MCP2518FD provides plug-and-play deployment but cannot scale to multi-channel or custom protocol extensions.

Availability

EF R-DI-CANFD-XC-SITE is available at Aetrix Electronics and suitable for automotive body control units, industrial sensor gateways, and instrument cluster communication hubs requiring stable component supply, long-term FPGA IP licensing, and Vivado toolchain support.

Supply support for EFR-DI-CANFD-XC-SITE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now part of AMD) is a semiconductor company specializing in adaptive computing platforms, including FPGAs, MPSoCs, and AI accelerators for aerospace, automotive, and industrial markets.

EF R-DI-CANFD-XC-SITE belongs to the LogiCORE IP portfolio - a suite of verified, licensable IP cores designed to accelerate protocol implementation in Xilinx devices while ensuring standards compliance and toolchain integration.

FAQ

What is the licensing requirement for deploying EFR-DI-CANFD-XC-SITE in production?

EF R-DI-CANFD-XC-SITE requires a valid Bosch CAN FD protocol license for commercial sale of end devices. The license is separate from Xilinx IP licensing and must be obtained directly from Bosch. Vivado synthesis and implementation enforce license checks; generation halts without a valid key. EFR-DI-CANFD-XC-SITE itself is delivered as encrypted RTL under the CAN FD LogiCORE IP License Agreement for Automotive or Non-Automotive use.

Does EFR-DI-CANFD-XC-SITE support both ISO and non-ISO CAN FD frame formats?

Yes, EFR-DI-CANFD-XC-SITE supports both ISO 11898-1:2015 and Bosch non-ISO CAN FD frame formats. Selection is parameterized during core customization in Vivado IP Catalog. This dual-format capability enables interoperability with legacy Bosch-spec ECUs and newer ISO-compliant nodes in mixed-protocol automotive networks.

How is the EFR-DI-CANFD-XC-SITE clock domain crossing managed between host and CAN layers?

EF R-DI-CANFD-XC-SITE uses CDC synchronizers to bridge the AXI4-Lite clock domain (s_axi_aclk) and the CAN clock domain (can_clk). The Object Layer (registers, buffer managers) operates in s_axi_aclk, while the Transfer Layer (bit timing, protocol engine) runs in can_clk. All inter-layer data transfers - including TX buffer handoff and RX FIFO writes - pass through hardened synchronizer circuits to prevent metastability.

What buffer configurations does EFR-DI-CANFD-XC-SITE support for RX message handling?

EF R-DI-CANFD-XC-SITE supports two RX modes: Sequential (FIFO) mode with 32-deep message storage and 32 ID filter-mask pairs, and Mailbox mode supporting up to 48 independent RX buffers. Mode selection is static at configuration time. FIFO mode ensures strict priority-by-ID ordering; Mailbox mode enables dedicated storage for critical message types like diagnostics or safety commands.

Can EFR-DI-CANFD-XC-SITE operate without an external CAN transceiver?

No, EFR-DI-CANFD-XC-SITE requires an external CAN FD transceiver (e.g., NXP TJA1042, TI TCAN1042) connected to can_phy_tx and can_phy_rx signals. The core implements only the protocol engine and link layer - physical layer signaling, common-mode rejection, and bus termination are handled entirely by the transceiver. This separation enables flexible PHY selection based on voltage, fault tolerance, and EMC requirements.