AMD EFR-DI-CANFD-XC-WW

Overview

EFR-DI-CANFD-XC-WW from Xilinx is a LogiCORE IP soft core implementing the ISO 11898-1:2015 CAN FD protocol for FPGA-based automotive and industrial communication systems. It supports dual-rate operation (nominal up to 1 Mbps, data phase >4 Mbps), 64-byte payload frames, AXI4-Lite host interface, and configurable TX/RX mailbox or FIFO buffering - deployed in Zynq-7000, UltraScale, and UltraScale+ FPGAs for body control units and sensor networks.

For engineers reviewing the EFR-DI-CANFD-XC-WW datasheet, pinout, applications, or equivalent options, this IP core delivers certified ISO CAN FD frame handling, hardware-accelerated bit timing control, transmitter delay compensation, and integrated error logging - with mandatory Bosch license compliance for commercial deployment.

Technical Context

The EFR-DI-CANFD-XC-WW implements a layered architecture: an AXI4-Lite Object Layer (in host clock domain) manages register access, TX/RX buffer arbitration, and message scheduling; a Transfer Layer (in CAN clock domain) handles physical layer interfacing, bit stuffing/de-stuffing, CRC calculation including stuff-bit count for FD frames, bit rate switching, and error detection per ISO 11898-1:2015.

It supports three operational modes beyond Normal: Snoop mode (bus monitoring without ACK), Loopback mode (internal TX→RX path), and Sleep mode with Wake-up interrupt. Clocking requires separate s_axi_aclk (AXI domain) and can_clk (CAN domain) inputs; CDC synchronizers bridge inter-domain data transfers between layers.

Key Specifications

Pinout & Package

This is a soft IP core - no physical package or pins. It is implemented as encrypted RTL targeting Xilinx FPGAs and interfaces via defined signal ports.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CAN FD protocol engine applications.

Compared with Xilinx LogiCORE IP CAN v2.0 and NXP S32K144, the EFR-DI-CANFD-XC-WW uniquely delivers ISO-certified CAN FD acceleration in programmable logic - enabling scalable bandwidth, runtime reconfiguration, and co-processing with custom accelerators in Zynq or UltraScale+ platforms.

Availability

EFR-DI-CANFD-XC-WW is available at Aetrix Electronics and suitable for automotive body control units, industrial sensor networks, HIL test equipment, and functional safety gateways requiring stable component supply and long-term FPGA IP licensing support.

Supply support for EFR-DI-CANFD-XC-WW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now part of AMD) is a semiconductor company specializing in adaptive computing solutions, including FPGAs, SoCs, and IP cores for high-performance, low-latency applications.

The EFR-DI-CANFD-XC-WW belongs to the LogiCORE IP portfolio, designed specifically to accelerate ISO-compliant CAN FD protocol implementation in Xilinx FPGAs for automotive and industrial real-time communication systems.

FAQ

What is the licensing requirement for commercial use of EFR-DI-CANFD-XC-WW?

A valid Bosch CAN FD protocol license is mandatory before selling any device containing the EFR-DI-CANFD-XC-WW IP core. Xilinx enforces license checks during Vivado synthesis and implementation; generation halts without a verified license key. The core is offered under separate Automotive or Non-Automotive license agreements - contact AMD/Xilinx sales for terms and activation.

Does EFR-DI-CANFD-XC-WW include an integrated CAN transceiver?

No, the EFR-DI-CANFD-XC-WW is a digital logic IP core only. It requires connection to an external CAN FD transceiver (e.g., TI TCAN1042, NXP TJA1044) via can_phy_tx and can_phy_rx signals. The core handles protocol, timing, and buffering; physical layer signaling is fully offloaded to the transceiver.

Which Xilinx device families support EFR-DI-CANFD-XC-WW?

The EFR-DI-CANFD-XC-WW is validated for UltraScale+, UltraScale, Zynq-7000 All Programmable SoC, and 7 Series FPGAs. Full device compatibility is listed in the Vivado IP catalog; resource utilization varies by target family - e.g., Zynq-7000 implementations use ~1,200 LUTs and 2 BRAMs for baseline configuration.

How does EFR-DI-CANFD-XC-WW handle bit timing configuration?

The EFR-DI-CANFD-XC-WW uses two independent timing registers: BRPR/BTR for arbitration phase (nominal bit rate) and DP_BRPR/DP_BTR for data phase. Each supports programmable prescaler, SJW, TS1, and TS2 values per ISO 11898-1, enabling precise tuning for oscillator tolerance and bus length - all configured via AXI4-Lite writes to dedicated address-mapped registers.

Can EFR-DI-CANFD-XC-WW operate without a processor interface?

Yes - the EFR-DI-CANFD-XC-WW supports stand-alone operation using direct AXI4-Lite register access from custom logic (e.g., state machines or DMA controllers). It does not require MicroBlaze or ARM; however, software drivers are provided for both Standalone SDK and Linux environments when used with those processors.