AMD EFR-DI-CLAUSE74-FEC-PROJ

Overview

EF R-DI-CLAUSE74-FEC-PROJ from Xilinx is a LogiCORE IP core implementing IEEE 802.3 Clause 74 Forward Error Correction (KR FEC) for high-speed Ethernet and Fibre Channel PHYs. It performs full (2112,2080) Fire code encoding/decoding, corrects burst errors up to 11 bits, operates at up to 425 MHz (28 Gb/s), and integrates alignment, transcoding, and scrambling functions within a single hardened logic block for UltraScale™ and UltraScale+™ FPGAs.

For engineers reviewing the EFR-DI-CLAUSE74-FEC-PROJ datasheet, pinout, applications, or equivalent options, this IP core is selected for 10G/25G/40G/50G/100GBASE-R Ethernet and 16G Fibre Channel designs requiring deterministic latency, MDIO-configurable error indication, and transceiver gearbox slip coordination - not as a physical component but as a synthesizable, license-controlled RTL module.

Technical Context

The EFR-DI-CLAUSE74-FEC-PROJ implements a fully synchronous dual-domain architecture with independent tx_clk and rx_clk domains (up to 425 MHz), each with active-low reset (tx_resetn/rx_resetn). It processes 66-bit wide data streams aligned to IEEE 802.3-2015 Clause 74.7.4, using tx_din_start and rx_din_slip signals to control codeword boundaries and enable receiver alignment via transceiver gearbox bit-slip.

Latency is deterministic and mode-dependent: transmit encode requires exactly 5 clock cycles; receive decode latency is 71 cycles with error indication enabled and 45 cycles when bypassed. The core supports runtime configuration of ctrl_rx_indication_en and ctrl_rx_header_mark[31:0] without reset, enabling dynamic switching between error-marking and pass-through behavior for uncorrectable codewords.

Key Specifications

Availability

EF R-DI-CLAUSE74-FEC-PROJ is available at Aetrix Electronics and suitable for 10G/25G Ethernet PHY development, 16G Fibre Channel link design, and high-speed optical interconnect prototyping requiring stable component supply and long-term IP licensing continuity.

Supply support for EFR-DI-CLAUSE74-FEC-PROJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now part of AMD) is a semiconductor company specializing in programmable logic devices, FPGA-based system-on-chip solutions, and high-performance IP cores for wired communications, AI acceleration, and embedded vision.

EF R-DI-CLAUSE74-FEC-PROJ belongs to the LogiCORE IP portfolio targeting high-speed serial interface subsystems; it was designed specifically to offload IEEE-compliant FEC processing from soft logic, enabling deterministic timing closure and resource-efficient implementation in UltraScale™ and UltraScale+™ FPGAs.

FAQ

What is the EFR-DI-CLAUSE74-FEC-PROJ and how is it delivered?

EF R-DI-CLAUSE74-FEC-PROJ is a Xilinx LogiCORE IP core - not a physical IC - delivered as encrypted RTL (Verilog) and integrated into Vivado® Design Suite projects. It requires a commercial license for full hardware deployment; evaluation licenses may be available. The EFR-DI-CLAUSE74-FEC-PROJ is instantiated as a parameterless module with fixed port definitions and no user-configurable parameters.

Which FPGA families support the EFR-DI-CLAUSE74-FEC-PROJ?

The EFR-DI-CLAUSE74-FEC-PROJ is validated for UltraScale™ and UltraScale+™ FPGA families only, where it leverages dedicated transceiver infrastructure and routing resources. It is not supported on 7-series, Virtex-6, or earlier architectures. Device compatibility is verified through the Vivado IP catalog; all supported parts must include GTY/GTH transceivers capable of ≥10 Gb/s operation.

Does the EFR-DI-CLAUSE74-FEC-PROJ support Energy-Efficient Ethernet (EEE)?

No. The EFR-DI-CLAUSE74-FEC-PROJ explicitly excludes FEC rapid block synchronization (IEEE 802.3-2015 Section 74.7.4.8), which is required for EEE operation. This omission is documented as an unsupported feature in PG303 v1.0. Systems requiring EEE must implement alternative synchronization mechanisms outside the EFR-DI-CLAUSE74-FEC-PROJ core.

How does the EFR-DI-CLAUSE74-FEC-PROJ handle uncorrectable codewords?

When ctrl_rx_indication_en = 1, the EFR-DI-CLAUSE74-FEC-PROJ marks all 32 sync headers of an uncorrectable 2112-bit codeword as binary 11 (invalid) per IEEE 802.3-2015. When disabled (ctrl_rx_indication_en = 0), it passes raw received data without modification. The ctrl_rx_header_mark[31:0] vector allows selective header marking, giving designers precise control over error signaling behavior in the EFR-DI-CLAUSE74-FEC-PROJ.

What are the clocking requirements for the EFR-DI-CLAUSE74-FEC-PROJ?

The EFR-DI-CLAUSE74-FEC-PROJ requires two independent clocks: tx_clk (for encoder and transmit control) and rx_clk (for decoder and receive control), both with active-low resets (tx_resetn/rx_resetn). Nominal frequencies range from 156.25 MHz (10GE) to 425 MHz (28 Gb/s). Clocks must be stable before reset release; domain-crossing signals are not internally synchronized.