AMD EF-SDSOC-NL

Overview

EF-SDSOC-NL from Xilinx is a non-license version of the SDSoC™ Development Environment, a C/C++-based integrated design suite for Zynq®-7000 SoC and Zynq UltraScale+™ MPSoC platforms. It enables software developers to accelerate functions in programmable logic, perform system-level profiling, and generate full hardware/software systems from a single source - supporting bare-metal, Linux, and FreeRTOS targets on validated boards including ZC702, ZC706, ZedBoard, and MicroZed.

For engineers reviewing the EF-SDSOC-NL datasheet, EF-SDSOC-NL application, EF-SDSOC-NL equivalent, or EF-SDSOC-NL pinout, this tool delivers ASSP-like embedded development for heterogeneous SoC platforms - with emphasis on rapid C/C++ acceleration, automated AXI connectivity synthesis, ARM + PL co-design, and platform-based performance estimation without RTL expertise.

Technical Context

The EF-SDSOC-NL provides a full-system optimizing compiler that targets both ARM-based processing systems and programmable logic, using high-level synthesis (HLS) technology to transform annotated C/C++ into hardware accelerators and software drivers. It integrates with Vivado Design Suite for bitstream generation and SDK for ARM-side compilation.

System-level profiling in EF-SDSOC-NL leverages non-intrusive PC sampling and ARM performance counters, augmented by automatically inserted AXI Performance Monitors (APM) in programmable logic - enabling cycle-accurate estimation of software/hardware execution time, data transfer overhead, and resource utilization before hardware implementation.

Key Specifications

Availability

EF-SDSOC-NL is available at Aetrix Electronics and suitable for embedded prototyping, academic research, SoC architecture exploration, and pre-commercial FPGA-accelerated application development requiring stable component supply and toolchain continuity.

Supply support for EF-SDSOC-NL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx, Inc. is a U.S.-based semiconductor company specializing in adaptive computing solutions, acquired by AMD in 2022. It pioneered the All Programmable SoC architecture combining ARM processors with FPGA fabric.

The EF-SDSOC-NL belongs to Xilinx's SDx™ family of software-defined development environments, designed specifically to lower the barrier to entry for C/C++ developers targeting heterogeneous Zynq platforms - enabling hardware acceleration without RTL expertise.

FAQ

What is the functional scope of EF-SDSOC-NL compared to the licensed SDSoC product?

The EF-SDSOC-NL provides identical core functionality - C/C++ acceleration, system-level profiling, full-system compilation, and BSP support - as the commercial SDSoC license. However, EF-SDSOC-NL lacks deployment rights and is restricted to evaluation, education, and internal prototyping use per Xilinx's terms. It does not support production bitstream generation or commercial redistribution of generated hardware/software artifacts.

Which Zynq platforms are officially supported by EF-SDSOC-NL?

EF-SDSOC-NL supports Zynq-7000 SoCs (e.g., Z-7020 on ZC702, Z-7030 on ZC706) and Zynq UltraScale+ MPSoCs (e.g., ZU9EG on ZCU102, ZU7EV on ZCU104), with validated Board Support Packages for ZC702, ZC706, ZedBoard, MicroZed, and ZYBO. Platform metadata ensures correct clocking, memory mapping, and peripheral configuration during build.

Does EF-SDSOC-NL require Vivado Design Suite to operate?

Yes, EF-SDSOC-NL requires Vivado Design Suite (2015.4 or later) as a backend toolchain for programmable logic synthesis, place-and-route, and bitstream generation. The EF-SDSOC-NL IDE invokes Vivado automatically during hardware build steps but does not include Vivado licensing - users must obtain separate Vivado WebPACK or licensed editions.

Can EF-SDSOC-NL generate accelerators for custom IP or legacy HDL blocks?

Yes, EF-SDSOC-NL supports integration of legacy HDL IP as C-callable libraries via the Platform Creation workflow. Users can wrap existing Verilog/VHDL modules with AXI-4 Lite or AXI-Stream interfaces and expose them as callable functions in C/C++, enabling reuse of verified IP alongside newly accelerated functions within the same application.

Is EF-SDSOC-NL compatible with Linux-based host development environments?

Yes, EF-SDSOC-NL runs on Linux (RHEL/CentOS 6.5+, Ubuntu 14.04+) and Windows 7/10 (64-bit). Its Eclipse-based IDE supports cross-compilation for ARM targets, and all profiling, compilation, and deployment workflows function identically across supported host OSes - provided Vivado and required toolchains are installed and licensed.