Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > PFC (Power Factor Correction)

STMicroelectronics E-L6563

Name: E-L6563
Brand: STMicroelectronics
SKU: E-L6563
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: E-L6563

Manufacturer:: STMicroelectronics

Category:: PFC (Power Factor Correction)

Package:: 14-SOIC (0.154", 3.90mm Width)

Datasheet:: E-L6563.pdf

Description:: IC PFC CTRLR TRANSITION 14SO

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,111

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

E-L6563 from STMicroelectronics is an advanced transition-mode (TM) power factor correction (PFC) controller in SO-14 package, designed for high-efficiency AC-DC pre-regulators. It delivers 1.5% internal reference voltage accuracy at 25°C, ≤90 µA start-up current, and a ±600/±800 mA totem-pole gate driver for direct MOSFET/IGBT drive. Its core function is precise output voltage regulation with tracking boost, input voltage feedforward (1/V²), and latched protection against feedback loop failure - deployed in >350W IEC61000-3-2-compliant server and HI-END adapter power supplies.

For engineers reviewing the E-L6563 datasheet, E-L6563 pinout, E-L6563 application, or E-L6563 equivalent, key selection criteria include its inductor saturation detection (exclusive to L6563 vs L6563A), dual OVP architecture (static + dynamic), PFC_OK latch signaling, and VFF-based RMS line sensing for THD optimization across universal mains input.

Technical Context

The E-L6563 implements current-mode control in transition mode using zero-current detection (ZCD) on pin 11 to trigger MOSFET turn-on at inductor demagnetization. Its multiplier circuit accepts rectified mains via MULT (pin 3) and RMS-derived feedforward via VFF (pin 5), enabling 1/V² gain compensation that stabilizes loop response across 85–265 VAC input.

It integrates dedicated protection logic: CS (pin 4) compares sensed current against 1.7 V to detect inductor saturation (latched shutdown), while PFC_OK (pin 7) monitors output voltage divider and asserts PWM_LATCH (pin 8) if >2.5 V - both functions absent in L6563A. RUN (pin 10) enables brownout detection when tied to VFF.

Key Specifications

Parameter	Value and Actual Design Meaning
Control Mode	Transition-mode (TM) current-mode with ZCD-triggered MOSFET turn-on - ensures soft-switching and low EMI in boost PFC stages.
Reference Voltage	1.5% accuracy @ TJ = 25°C - enables tight output voltage regulation without external trimming in 380–400 VDC PFC outputs.
Start-up Current	≤90 µA @ VCC = 10 V - allows use of high-value, cost-effective start-up resistors and reduces no-load losses.
Gate Driver	±600 mA source / ±800 mA sink - directly drives high-Qg MOSFETs (e.g., 20 nC) without external buffers in >350W designs.
OVP Architecture	Dual-level: static threshold at 2.15 V (PFC_OK pin), dynamic triggering at 20 µA (IOVP) - prevents false trips during transients while ensuring fast fault response.
Voltage Feedforward	1/V² correction via VFF pin - linearizes current loop gain across 85–265 VAC, maintaining <5% THD from 20–100% load.
Inductor Saturation Detect	CS pin comparator with 1.7 V latch-off threshold - halts switching and asserts PWM_LATCH upon core saturation, protecting MOSFET and diode.

Pinout & Package

SO-14 surface-mount package with standard JEDEC outline, 1.27 mm pitch, and thermal resistance R_thJA = 120 °C/W - compatible with automated assembly and supports continuous operation up to T_J = 125 °C under proper PCB copper area.

Pin/Terminal	Circuit Role	Design Meaning
1 (INV)	Inverting input of voltage error amplifier	Accepts resistor-divider feedback from PFC output; sinks programmable current from TBO pin for tracking boost functionality.
2 (COMP)	Error amplifier output	Drives multiplier input; requires external RC compensation network between COMP and INV to stabilize voltage loop and minimize THD.
3 (MULT)	Main multiplier input	Receives scaled rectified AC waveform; sets sinusoidal current reference shape for high PF (>0.99) across full load range.
4 (CS)	Current sense comparator input	Detects MOSFET conduction current; 1.7 V threshold triggers latched shutdown on inductor saturation (L6563 only).
5 (VFF)	Voltage feedforward input	Derives RMS line voltage via peak-hold circuit; enables 1/V² gain correction to maintain constant loop gain from 85–265 VAC.
6 (TBO)	Tracking Boost output	Buffered VFF voltage; sets current sunk from INV pin to dynamically scale PFC output voltage with AC line (e.g., 380 V @ 230 VAC → 340 V @ 115 VAC).
7 (PFC_OK)	Output voltage monitor / disable	Latches shutdown if >2.5 V (feedback failure); disables IC if <0.2 V - used for remote ON/OFF or brownout coordination with downstream PWM controller.
8 (PWM_LATCH)	Fault signaling output	Open-drain, high-impedance normal state; pulled high during PFC_OK or CS faults to disable downstream DC-DC converter with latched protection.
9 (PWM_STOP)	Temporary stop signaling	Pulled low when RUN pin <0.52 V - used for light-load disable of DC-DC stage to meet Energy Star standby requirements.
10 (RUN)	Remote ON/OFF control	0.6 V enable / 0.52 V disable thresholds; tied to VFF for automatic brownout shutdown below ~85 VAC RMS.
11 (ZCD)	Zero-current detection input	Senses boost inductor demagnetization; negative edge triggers MOSFET turn-on - essential for TM operation and efficiency optimization.
12 (GND)	Signal and gate driver ground	Common return for analog circuitry and 800 mA sink driver; requires low-impedance PCB plane to prevent noise coupling into ZCD/MULT paths.
13 (GD)	Gate driver output	Totem-pole output clamped at 12 V; drives MOSFET gate directly with 60 ns typical rise/fall time - minimizes switching losses in high-frequency TM operation.
14 (VCC)	Supply voltage input	10.3–22 V operating range; UVLO with 12 V turn-on / 9.5 V turn-off hysteresis - ensures reliable start-up and graceful shutdown during brownout.

Key Features

Feature	Design Value
Inductor saturation detection	Hardware-level CS pin comparator with 1.7 V latch-off threshold - eliminates need for external saturation sensing circuits and prevents MOSFET avalanche failure.
Tracking Boost function	Programmable output voltage scaling via TBO-to-INV current sink - enables adaptive output (e.g., 340–400 VDC) matching AC line variation, improving light-load efficiency.
1/V² voltage feedforward	VFF pin interface with internal peak-hold circuit - automatically compensates loop gain for line voltage changes, sustaining <5% THD from 85–265 VAC without recalibration.
Two-step overvoltage protection	Static OVP (2.15 V at PFC_OK) + dynamic OVP (20 µA injection) - distinguishes sustained overvoltage from transient spikes, preventing nuisance shutdowns.
Latched feedback failure protection	PFC_OK pin >2.5 V forces latched shutdown and asserts PWM_LATCH - guarantees downstream converter disable if output voltage runs away due to optocoupler or divider fault.

Applications

Server Power Supply

HI-END AC-DC Adapter

Use Scenario: 80 PLUS Platinum-certified 1200 W redundant power supply for rack-mounted servers requiring <5% THD and >94% efficiency at 50% load.

IC Role / Device Role / Timing Role: Primary PFC controller regulating 385 VDC bus; synchronizes boost switching via ZCD to achieve zero-voltage turn-on and minimize switching loss.

Use Value: 1/V² feedforward maintains stable current loop gain across 100–240 VAC input, enabling single design for global deployment without hardware revision.

Use Scenario: 300 W laptop charger with active PFC meeting IEC61000-3-2 Class D limits and Energy Star 6.1 standby power <0.3 W.

IC Role / Device Role / Timing Role: Transition-mode PFC pre-regulator driving 600 V MOSFET; uses RUN pin tied to VFF for automatic brownout disable below 85 VAC.

Use Value: ≤90 µA start-up current and 2.2 mA disabled-state quiescent current enable compliance with strict no-load power budgets.

Industrial SMPS

Medical AC-DC Module

Use Scenario: 500 W industrial control power supply operating continuously at 60°C ambient, requiring robust protection against line surges and component drift.

IC Role / Device Role / Timing Role: Core PFC controller with latched OVP and feedback failure detection; CS pin monitors boost current to prevent inductor saturation during cold-start inrush.

Use Value: Internal 1.5% reference and -25°C to +125°C guaranteed specs ensure output regulation stability across extended temperature range without calibration.

Use Scenario: 250 W medical-grade AC-DC module certified to IEC60601-1, requiring fail-safe shutdown on any PFC anomaly to protect patient-connected downstream circuits.

IC Role / Device Role / Timing Role: Safety-critical PFC supervisor; PWM_LATCH output hard-wires to downstream PWM controller's disable pin for immediate, latched shutdown on PFC_OK or CS fault.

Use Value: Dual OVP (static + dynamic) and latched protection provide redundant safety layers exceeding basic regulatory requirements for life-support equipment.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PFC controller applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
UCC28070	Continuous conduction mode (CCM) controller with average-current sensing; no ZCD or TM support; higher BOM cost due to current-sense transformer.	Targeted at >750 W industrial SMPS where CCM efficiency outweighs complexity; lacks tracking boost and inductor saturation detection.	Select UCC28070 only when CCM operation is mandated by EMI profile or when >750 W output necessitates lower peak currents.
L6563A	Pin-compatible variant omitting inductor saturation detection (no CS latch-off), identical electrical specs otherwise; same SO-14 footprint and pinout.	Used in cost-sensitive consumer adapters where saturation risk is mitigated by conservative inductor design and derating.	Choose L6563A for non-critical applications with margin-controlled magnetics; retain E-L6563 where field reliability under overload or aging is mandatory.

Compared with UCC28070, E-L6563 offers lower system cost and simpler layout via TM operation and integrated ZCD, while L6563A trades away critical fault protection for marginal BOM reduction - making E-L6563 the optimal choice for robust, mid-power PFC where safety and THD consistency are prioritized.

Availability

E-L6563 is available at Aetrix Electronics and suitable for server power supplies, HI-END AC-DC adapters, and industrial SMPS requiring stable component supply, long-term lifecycle assurance, and guaranteed traceability for medical and telecom applications.

Supply support for E-L6563 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, power, microcontroller, and sensor solutions for industrial, automotive, and consumer markets.

E-L6563 belongs to ST's legacy PFC controller product line, engineered specifically for high-efficiency, low-THD transition-mode boost pre-regulators targeting >350W IEC61000-3-2-compliant power systems.

FAQ

What is the functional difference between E-L6563 and E-L6563A?

The sole functional difference is inductor saturation detection: E-L6563 includes a 1.7 V latch-off comparator on the CS pin that shuts down the IC and asserts PWM_LATCH upon saturation, while E-L6563A omits this feature. All other electrical characteristics, pinout, and package are identical - making E-L6563A a cost-reduced variant for applications with conservative magnetic design.

How does the Tracking Boost function adjust PFC output voltage?

Tracking Boost uses a buffered VFF voltage on pin 6 (TBO) to sink programmable current from pin 1 (INV). This current reduces the effective feedback voltage at INV, causing the error amplifier to raise the output voltage proportionally to the RMS line voltage - e.g., scaling from 340 VDC at 115 VAC to 400 VDC at 230 VAC, improving light-load efficiency without manual adjustment.

Can E-L6563 drive a 600 V, 25 nC MOSFET directly?

Yes - the ±600 mA source / ±800 mA sink totem-pole gate driver (pin 13) provides sufficient peak current to charge/discharge a 25 nC gate within 60 ns (t_r/t_f), and the 12 V output clamp prevents gate oxide overstress. Layout best practices (short gate traces, local 100 nF decoupling at VCC/GD) are required to maintain switching integrity.

What protection mechanisms activate during PFC feedback loop failure?

Feedback loop failure triggers two coordinated protections: (1) PFC_OK pin (7) detects overvoltage >2.5 V and initiates latched shutdown, reducing consumption to 250 µA; (2) PWM_LATCH pin (8) is asserted high to disable the downstream DC-DC PWM controller - ensuring complete system halt without requiring software intervention or external supervision.

E-L6563 Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 14-SOIC (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Obsolete

Mode:: Discontinuous (Transition)

Frequency - Switching:: -

Current - Startup:: 50 µA

Voltage - Supply:: 10.3V ~ 22V

Operating Temperature:: -25°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-SO

E-L6563 FAQ

1.How can I place an order for E-L6563 through Aetrix?

Please submit a Request for Quotation (RFQ) for E-L6563 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for E-L6563 reliable?

The price and inventory of E-L6563 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for E-L6563 is usually 5 days.

3.What payment methods are accepted for E-L6563?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for E-L6563 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for E-L6563?

E-L6563 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your E-L6563 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for E-L6563?

For technical support, including E-L6563 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your E-L6563 requirements.

6.How does Aetrix verify that E-L6563 is sourced from the original manufacturer or authorized distributors?

All E-L6563 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that E-L6563 meets industry standards.

7.What is the process for return or replacement of E-L6563?

All E-L6563 units undergo pre-shipment inspection (PSI). If there is an issue with E-L6563, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The E-L6563 part is unused and in its original packaging.

Return procedure for E-L6563:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…