Analog Devices Inc. EV1HMC6787ALC5A
- Part No.:
- EV1HMC6787ALC5A
- Manufacturer:
- Analog Devices Inc.
- Category:
- RF, RFID, Wireless Evaluation Boards
- Package:
- Datasheet:
-
EV1HMC6787ALC5A.pdf
- Description:
- EVAL BOARD HMC6787ALC5A PCB ASSY
- Quantity:
- Payment:

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Product details
Overview
HMC6787ALC5A from Analog Devices (formerly Hittite Microwave) is a GaAs MMIC I/Q upconverter IC operating in the 37–40 GHz RF band, delivering 10 dB typical conversion gain, 17 dBc sideband rejection, and 13 dB of analog gain control via VCTRL. It integrates an RF variable-gain amplifier and I/Q mixer with internal X2 LO multiplier, requiring only an external IF 90° hybrid for sideband selection-enabling compact SSB upconversion in point-to-point radio and satellite communications systems.
For engineers reviewing the HMC6787ALC5A datasheet, HMC6787ALC5A pinout, HMC6787ALC5A application, or HMC6787ALC5A equivalent, this page provides verified RF performance data, validated DC biasing conditions, confirmed 16-pin 5×5 mm ceramic SMT package mapping, and two field-validated alternative upconverters for millimeter-wave SSB designs.
Technical Context
The HMC6787ALC5A implements a direct-conversion I/Q upconversion architecture with integrated LO frequency doubling (X2), enabling operation from 16.5–22 GHz LO input to generate 37–40 GHz RF output. Its dual IF inputs (IF1/IF2) accept baseband or low-IF signals up to 4 GHz, while sideband suppression relies on precise quadrature phase alignment via external 90° hybrid.
Gain control is achieved through a dedicated VCTRL pin (−3.5 V to 0 V), adjusting conversion gain over 13 dB range without altering LO or RF matching. Biasing uses separate VGLO (−1 V to 0 V) and VGRF (−1 V to 0 V) controls to set IDLO = 150 mA and IDRF = 200 mA, with all supply voltages fixed at +3 V (VDLO1, VDLO2, VDRF).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RF Frequency Range | 37–40 GHz - supports E-band wireless infrastructure and satellite uplinks. |
| LO Frequency Range | 16.5–22 GHz - enables use with commercial 18 GHz LO sources and eliminates need for higher-frequency synthesizers. |
| IF Frequency Range | DC–4 GHz - accommodates baseband I/Q or low-IF architectures up to C-band. |
| Conversion Gain | 10 dB typ. - reduces cascaded noise figure in multi-stage transmitters. |
| Sideband Rejection | 17 dBc typ. - lowers post-upconversion filtering requirements when paired with external 90° hybrid. |
| OIP3 | +26 dBm typ. - supports high-linearity operation in spectrally dense E-band links. |
| 1 dB Compression (P1dB) | +14 dBm typ. - defines usable dynamic range before gain compression degrades modulation fidelity. |
| LO–RF Isolation | 15 dB min. - mitigates LO leakage into antenna path, easing front-end filter design. |
Pinout & Package
16-lead 5×5 mm RoHS-compliant ceramic SMT package (alumina body, gold-over-nickel plating, MSL3 rating). Exposed ground paddle must be soldered to PCB RF ground per JEDEC standards.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | VCTRL | Analog gain control input; −3.5 V to 0 V sets 13 dB gain range; draws <1 mA. |
| 2, 3 | IF1, IF2 | Differential I/Q baseband/low-IF inputs; DC-coupled, ±3 mA max current sourcing/sinking. |
| 4, 5, 6 | N/C | No internal connection; externally grounded for RF stability and thermal conduction. |
| 7, 9 | VDLO1, VDLO2 | +3 V bias for LO multiplier buffer stages; sets LO path quiescent current. |
| 8, 10, 16 | GND | RF/DC ground terminals; must connect to PCB ground plane and exposed paddle. |
| 11 | LOIN | LO input port; accepts 0–8 dBm drive; internal X2 multiplier generates 2×LO for mixing. |
| 12 | VGLO | Bias control for LO multiplier; −1 V to 0 V adjusts IDLO to 150 mA (200–230 mA with LO drive). |
| 13 | VGRF | Bias control for RF VGA; −1 V to 0 V sets IDRF to 200 mA. |
| 14 | RFOUT | Single-ended RF output; 37–40 GHz SSB signal; requires 50 Ω matched transmission line. |
| 15 | VDRF | +3 V bias for RF variable-gain amplifier stage. |
Key Features
| Feature | Design Value |
|---|---|
| I/Q upconversion with X2 LO multiplier | Eliminates need for external 2× multiplier IC or fundamental 37–40 GHz LO source. |
| 13 dB analog gain control via VCTRL | Enables closed-loop power control without digital interface or external attenuators. |
| 17 dBc sideband rejection (typ.) | Reduces image filter order and insertion loss in SSB transmitter chains. |
| 16-lead 5×5 mm ceramic SMT package | Supports automated assembly and achieves <55 °C/W thermal resistance to ground paddle. |
| DC-coupled IF inputs | Permits zero-IF modulation schemes and simplifies baseband DAC interfacing. |
| −40°C to +85°C operating temperature | Validated for outdoor wireless infrastructure and airborne radar subsystems. |
Applications
| Point-to-Point Radio | Satellite Communications Uplink |
|---|---|
Use Scenario: High-capacity backhaul link operating in E-band (38 GHz licensed spectrum) with QPSK/16-QAM modulation. IC Role / Device Role / Timing Role: I/Q upconverter generating single-sideband RF output from baseband I/Q signals. Use Value: 17 dBc sideband rejection minimizes adjacent-channel interference; 10 dB gain reduces driver amplifier requirements. |
Use Scenario: Ground station uplink transmitter converting L-band IF to 37.5–40 GHz for geostationary satellite feeder links. IC Role / Device Role / Timing Role: Final-stage SSB upconverter with external 90° hybrid selecting upper sideband. Use Value: +26 dBm OIP3 maintains EVM under high-power spectral density; 5×5 mm footprint saves PCB area in constrained RF modules. |
| Military Radar Transmitter | Electronic Warfare (EW) Jammer |
Use Scenario: Active electronically scanned array (AESA) radar front-end requiring fast-agile, low-phase-noise upconversion. IC Role / Device Role / Timing Role: Compact SSB upconverter in T/R module, driven by stable 18 GHz LO synthesizer. Use Value: Integrated X2 multiplier avoids discrete multiplier losses; 13 dB gain control enables real-time output power leveling. |
Use Scenario: Wideband jammer generating deceptive signals across 37–40 GHz with rapid frequency hopping. IC Role / Device Role / Timing Role: I/Q modulator-based upconverter supporting complex waveform synthesis. Use Value: DC-coupled IF inputs enable arbitrary waveform generator (AWG) interfacing; 4 GHz IF bandwidth supports wide instantaneous bandwidth. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar I/Q upconverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HMC6300LP5E | 37–40 GHz RF, but uses fundamental LO (no X2 multiplier); requires 37–40 GHz LO source. | Lacks integrated LO multiplication; increases system complexity and LO chain loss. | Choose when ultra-low LO phase noise is critical and 37–40 GHz LO generation is already available. |
| Qorvo QPB1022 | 37–40 GHz RF, 18–22 GHz LO, but no analog gain control; fixed conversion gain of 8 dB. | Requires external VGA or attenuator for power management; no VCTRL pin. | Choose for cost-sensitive, fixed-gain applications where gain control is handled upstream. |
Compared with HMC6787ALC5A, HMC6300LP5E shifts LO burden to the system designer while offering marginally better phase noise, whereas QPB1022 trades gain adjustability for simplified biasing-making HMC6787ALC5A optimal for compact, self-contained SSB upconverters needing analog power control.
Availability
HMC6787ALC5A is available at Aetrix Electronics and suitable for point-to-point radio, satellite communications uplinks, and military radar transmitters requiring stable component supply across extended temperature ranges and high-frequency reliability.
Supply support for HMC6787ALC5A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Hittite Microwave in 2014 and maintains its high-frequency RF product lines, including GaAs MMICs for defense, aerospace, and wireless infrastructure.
The HMC6787ALC5A belongs to Analog Devices' millimeter-wave upconverter family, designed specifically for compact, high-linearity SSB signal generation in E-band communication and sensing systems.
FAQ
What is the required LO drive level for HMC6787ALC5A?
HMC6787ALC5A requires LO input power between 0 dBm and +8 dBm at 16.5–22 GHz. Performance data-including 10 dB conversion gain and 17 dBc sideband rejection-is specified at +4 dBm LO drive. Lower drive reduces conversion gain; exceeding +8 dBm risks damage per absolute maximum ratings.
Does HMC6787ALC5A require an external 90° hybrid?
Yes, HMC6787ALC5A requires an external IF 90° hybrid connected to IF1 and IF2 inputs to select the desired sideband (USB or LSB). The device's I/Q topology relies on external phase quadrature; no internal hybrid is integrated.
How is gain controlled on HMC6787ALC5A?
HMC6787ALC5A uses analog voltage control: applying −3.5 V to VCTRL (Pin 1) yields maximum conversion gain, while 0 V gives minimum gain-providing 13 dB of adjustable range. Current draw is <1 mA, enabling simple DAC or potentiometer control.
What are the DC bias requirements for HMC6787ALC5A?
HMC6787ALC5A requires three +3 V supplies (VDLO1, VDLO2, VDRF), plus two adjustable bias voltages: VGLO (Pin 12) and VGRF (Pin 13), each tuned from −1 V to 0 V to set IDLO = 150 mA and IDRF = 200 mA respectively. All grounds (Pins 8, 10, 16 and paddle) must connect to low-inductance RF ground.
Is HMC6787ALC5A compatible with DC-coupled baseband interfaces?
Yes, IF1 and IF2 inputs are DC-coupled and support operation down to 0 Hz. However, input current must remain within ±3 mA to avoid forward-biasing internal ESD diodes-requiring careful DAC output stage design or AC coupling if DC offset exceeds safe limits.
EV1HMC6787ALC5A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Packaging:
- Box
- Product Status:
- Active
- Type:
- Upconverter
- Frequency:
- 37GHz ~ 40GHz
- Contents:
- Board(s)
- Utilized IC / Part:
- HMC6787ALC5A
EV1HMC6787ALC5A FAQ
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7.What is the process for return or replacement of EV1HMC6787ALC5A?
All EV1HMC6787ALC5A units undergo pre-shipment inspection (PSI). If there is an issue with EV1HMC6787ALC5A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The EV1HMC6787ALC5A part is unused and in its original packaging.
Return procedure for EV1HMC6787ALC5A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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