Analog Devices Inc. EVAL-AD1955EBZ

Overview

EVAL-AD1955EBZ from Analog Devices is an evaluation board for the AD1955 high-performance 24-bit stereo multibit sigma-delta DAC, supporting PCM up to 192 kHz and native DSD (64fS/128fS) SACD playback. It features differential current outputs (8.64 mA p-p), 120 dB A-weighted SNR at 48 kHz, –110 dB THD+N, and on-chip clickless volume/mute control via SPI. The board enables full validation of audio system integration in high-end DVD-Audio, SACD, and studio-grade digital mixing applications.

For engineers reviewing the EVAL-AD1955EBZ datasheet, EVAL-AD1955EBZ pinout, EVAL-AD1955EBZ application, or EVAL-AD1955EBZ equivalent, this board provides hardware-accessible test points for MCLK, LRCLK/BCLK/SDATA, DSD interface signals (DSD_SCLK/DSD_LDATA/DSD_RDATA/DSD_PHASE), analog IOUTL±/IOUTR± outputs, and SPI control lines (CCLK/CLATCH/CDATA), enabling real-time register configuration, zero-flag monitoring (ZEROL/ZEROR), and power-down/reset verification.

Technical Context

The EVAL-AD1955EBZ implements the full signal chain of the AD1955 IC: dual-channel multibit sigma-delta modulation with "Perfect Differential Linearity Restoration", 8×/4×/2× digital interpolation filtering, and data-directed scrambling for jitter immunity. It supports three operational modes-PCM (16–24-bit, 32–192 kHz), External Digital Filter (8fS/4fS/2fS), and SACD (64fS/128fS normal or phase mode)-with configurable master clock (256fS/512fS/768fS) and flexible serial port formats (I²S, left/right-justified, DSP).

Hardware-level features include on-board passive I/V conversion using AD797 op-amps, 2.80 V bias voltage generation, FILTR/FILTB reference decoupling (10 µF + 0.1 µF), and discrete zero-detection flag monitoring. The board exposes all 28 pins of the AD1955 in 28-lead SSOP package via test points and headers, with dedicated jumpers for MUTE, PD/RST, and ZEROL/ZEROR polarity selection.

Key Specifications

Availability

EVAL-AD1955EBZ is available at Aetrix Electronics and suitable for high-fidelity audio design validation, SACD playback system prototyping, and professional studio DAC architecture evaluation requiring stable component supply and full functional access to AD1955 registers and analog/digital I/O.

Supply support for EVAL-AD1955EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with deep expertise in precision audio, RF, and converter technologies.

The EVAL-AD1955EBZ belongs to Analog Devices' Audio Evaluation Platform family, designed specifically to accelerate development of premium consumer and professional audio systems leveraging their flagship high-resolution DACs like the AD1955.

FAQ

What is the primary function of the EVAL-AD1955EBZ evaluation board?

The EVAL-AD1955EBZ is a fully assembled and tested evaluation platform for the AD1955 24-bit stereo multibit sigma-delta DAC. It enables engineers to validate PCM and DSD audio playback performance, configure SPI-controlled registers (volume, mute, sample rate, de-emphasis), monitor zero-detection flags (ZEROL/ZEROR), and evaluate analog output behavior using on-board AD797-based I/V circuitry. The board directly interfaces with standard audio sources and measurement equipment.

Does the EVAL-AD1955EBZ support native DSD (SACD) playback, and how is it configured?

Yes, the EVAL-AD1955EBZ fully supports native DSD playback via the AD1955's dedicated SACD interface. It accepts 64fS (2.8224 MHz) or 128fS (5.6448 MHz) DSD bitstreams using DSD_SCLK, DSD_LDATA, DSD_RDATA, and DSD_PHASE pins. Configuration is performed through AD1955 Control Register 1 (Bits 6–7), selecting Normal or Phase Mode and 64fS/128fS bit rate. The board exposes all DSD signals for external decoder connection and includes pull-up resistors on DSD_SCLK/DSD_PHASE as specified in the AD1955 datasheet.

How does the EVAL-AD1955EBZ handle analog output interfacing, and what is the recommended I/V solution?

The EVAL-AD1955EBZ implements active I/V conversion using AD797 op-amps per channel, configured for differential-to-single-ended conversion with 6 VRMS output capability. It provides a 2.80 V bias voltage (VBIAS) referenced to VREFA for optimal THD+N performance across temperature. Passive I/V conversion is explicitly discouraged per AD1955 documentation; the board's design ensures proper bias current sinking (–3.24 mA per output) and maintains 100 pF output capacitance compliance. Test points allow direct probing of IOUTL±/IOUTR± before I/V stage.

Can the EVAL-AD1955EBZ be used to verify zero-detection and mute functionality of the AD1955?

Yes, the EVAL-AD1955EBZ provides direct access to ZEROL (Pin 21) and ZEROR (Pin 20) zero-detection flags and the MUTE (Pin 22) input. These signals are routed to test points and jumper-selectable headers, allowing real-time observation of flag assertion during silent PCM frames (1024 LRCLK periods) or SACD mute pattern detection (~22 ms). MUTE can be asserted via onboard jumper or external logic, enabling verification of clickless muting and full-scale attenuation (–100 dB) as specified in AD1955 electrical characteristics.

What clocking options does the EVAL-AD1955EBZ support for the AD1955, and how are they implemented?

The EVAL-AD1955EBZ supports all AD1955 master clock (MCLK) configurations: 256fS, 512fS, and 768fS (where fS = 44.1 kHz), selectable via solder jumpers or external source injection. MCLK (Pin 27) is accessible via SMA connector and test point. The board also routes LRCLK/EF_WCLK (Pin 2), BCLK/EF_BCLK (Pin 3), and DSD_SCLK (Pin 6) to dedicated headers, enabling synchronous operation with external DAC controllers, SACD decoders, or AES/EBU receivers. All timing parameters comply with AD1955 digital timing specifications (e.g., tDMP ≥ 50 ns, tDBP ≥ 60 ns).