STMicroelectronics EVALSTGAP1AS

Overview

EVALSTGAP1AS from STMicroelectronics is an automotive-grade evaluation board for the STGAP1AS galvanically isolated single-channel IGBT/MOSFET gate driver, supporting 1500 V high-voltage rail operation, 5 A sink/source drive capability, and SPI-configurable protection features including desaturation detection, active Miller clamp, and 2-level turn-off. It enables rapid validation of high-reliability inverter designs for EV traction inverters and industrial motor drives.

For engineers reviewing the EVALSTGAP1AS datasheet, EVALSTGAP1AS pinout, EVALSTGAP1AS application, or EVALSTGAP1AS equivalent, this board provides full access to the STGAP1AS's diagnostic status outputs, programmable deadtime, UVLO/OVLO thresholds, thermal warning signals, and SPI register interface - all critical for functional safety validation and AEC-Q100-compliant system integration.

Technical Context

The EVALSTGAP1AS implements a complete half-bridge test platform with isolated power supplies for both low- and high-side domains, enabling direct evaluation of STGAP1AS's galvanic isolation (UL 1577 certified, 5 kVRMS), ±50 V/ns dV/dt immunity, and 100 ns total propagation delay. It supports configurable gate drive configurations via external resistors and jumper settings.

Board-level features include dedicated test points for SENSE, DESAT, VCECLAMP, and DIAG outputs; on-board 3.3 V LDOs for logic and isolated sections; and hardware RESET/STOP command inputs aligned with STGAP1AS's functional safety architecture per ISO 26262 ASIL-B readiness requirements.

Key Specifications

Availability

EVALSTGAP1AS is available at Aetrix Electronics and suitable for EV traction inverter development, industrial servo drive qualification, and solar inverter reference design requiring stable component supply and full functional safety validation support.

Supply support for EVALSTGAP1AS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and power management solutions with strong IP in isolation technology and functional safety.

The EVALSTGAP1AS belongs to ST's Automotive Gate Driver Evaluation Platform family, designed specifically to accelerate ASIL-B-compliant inverter development by exposing all STGAP1AS protection, configuration, and diagnostic capabilities in a production-representative layout.

FAQ

Does EVALSTGAP1AS support daisy-chained SPI configuration for multi-driver systems?

Yes. The board includes dedicated SPI header pins (SCLK, MOSI, MISO, CS) and supports daisy-chain topology as documented in ST's AN5194 application note. Jumper-selectable CS routing and termination resistors allow seamless integration with up to four STGAP1AS devices sharing one SPI bus while maintaining CRC integrity and fault-isolation boundaries.

Can EVALSTGAP1AS be used to validate STGAP1AS's 2-level turn-off (2LTO) behavior under fault conditions?

Yes. The board provides direct access to the STGAP1AS's FAULT pin and DIAG output, and includes test points for gate voltage monitoring during forced desaturation events. Using the onboard SENSE and DESAT input circuitry, users can trigger and observe 2LTO waveforms - including short-turn-on pulses (mode "Always") and controlled turn-off sequences (mode "Fault") - with oscilloscope probes.

What power supply requirements must be met to operate EVALSTGAP1AS with full protection functionality enabled?

EVALSTGAP1AS requires two independent supplies: 5 V ±5 % @ ≥500 mA for the low-voltage domain (VDD), and 15 V ±10 % @ ≥200 mA for the high-voltage domain (VH). Both supplies must be electrically isolated. Failure to meet UVLO thresholds (VDD = 4.5 V, VH = 13.5 V) disables protection features and forces the device into safe state, as verified by STATUS1 register bit 0.

Is thermal shutdown testing supported on EVALSTGAP1AS without external heating equipment?

Yes. The board integrates a thermistor-based thermal sensing circuit connected to the STGAP1AS's THERM pin. Users can simulate temperature rise by applying a variable resistor (0–10 kΩ) between THERM and GNDISO, directly triggering thermal warning (TWARN) and shutdown (TSD) flags readable via SPI STATUS2 register bits 4 and 5 - eliminating need for hot-air rework stations during functional safety verification.