STMicroelectronics EVALSTGAP2HSCM

Overview

EVALSTGAP2HSCM from STMicroelectronics is a demonstration board for the STGAP2HSCM isolated 4 A single gate driver IC, designed to evaluate high-voltage half-bridge power stages up to 1200 V with TO-220/TO-247 IGBTs or MOSFETs. It integrates dual isolated DC-DC converters (5.2 kV isolation), supports configurable gate drive voltages (+15/0 V to +19/-3 V), and features onboard 3.3 V logic supply generation or external 5 V input.

For engineers reviewing the EVALSTGAP2HSCM datasheet, EVALSTGAP2HSCM pinout, EVALSTGAP2HSCM application, or EVALSTGAP2HSCM equivalent, this board enables rapid validation of negative gate driving, Miller clamp functionality, UVLO behavior, thermal shutdown response, and propagation delay (75 ns) under real high-side/high-voltage switching conditions.

Technical Context

The board implements a complete evaluation environment for the STGAP2HSCM gate driver IC, featuring galvanically isolated power delivery (5.2 kV) via two MGJ2D051509SC DC-DC converters-one for high-side (VH_H) and one for low-side (VH_L) gate supply-both fed by a single 5 V VAUX input. Dual independent input channels (IN+_H/IN-_H and IN+_L/IN-_L) support hardware interlocking and polarity selection.

It provides direct access to all critical signals-including GOUT, CLAMP, VH, GNDISO_H/L, and VDD-with test points (TP1–TP17), configurable jumpers (JP1–JP18), and socketed power devices (Q1/Q2). The layout enforces creepage/clearance compliance for 1200 V rail operation and includes EMI suppression (ferrite beads FB1–FB4) and HV-rated film capacitor C29 (33 nF/1.25 kV).

Key Specifications

Availability

EVALSTGAP2HSCM is available at Aetrix Electronics and suitable for industrial motor drives, renewable energy inverters, and uninterruptible power supplies requiring stable component supply, high-voltage gate driver validation, and fast-turnaround design iteration.

Supply support for EVALSTGAP2HSCM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, microcontrollers, and automotive-grade ICs with vertical manufacturing and broad industrial certification coverage.

EVALSTGAP2HSCM belongs to ST's high-voltage gate driver evaluation platform family, developed specifically to accelerate adoption of their STGAP series isolated drivers in ruggedized industrial power conversion designs.

FAQ

What power devices can be used with EVALSTGAP2HSCM?

The board supports TO-220 and TO-247 packaged N-channel IGBTs or MOSFETs rated up to 1700 V, as confirmed by Q1/Q2 footprint design and HV trace routing. Component values (e.g., R1/R2 = 2R2 gate resistors, C29 = 33 nF/1.25 kV snubber) are optimized for fast-switching 1200 V half-bridge topologies.

Does EVALSTGAP2HSCM provide isolated power for both high-side and low-side drivers?

Yes - it integrates two MGJ2D051509SC isolated DC-DC converters: one supplies VH_H to the high-side driver (U1), the other supplies VH_L to the low-side driver (U2), each delivering ±15 V or ±19 V outputs with 5.2 kV isolation from VAUX and from each other.

How is hardware interlocking implemented on this board?

Dual independent input pairs (IN+_H/IN-_H and IN+_L/IN-_L) allow cross-connected control logic; for example, connecting IN-_H to IN+_L and IN-_L to IN+_H creates mutual disable behavior. This prevents simultaneous conduction during controller faults, as verified in schematic Figure 1.

Can the board operate with only 3.3 V logic supply, or is 5 V mandatory?

Either is supported: the board generates 3.3 V from VAUX using U3/U4 auxiliary circuitry (see Figure 2), but also accepts external 5 V directly at VDD pins. JP11 closed selects onboard regulation; open allows external 5 V injection - confirmed in Bill of Material Table 1 and schematic page 3.