STMicroelectronics EVALSTGAP2SICD

Overview

EVALSTGAP2SICD from STMicroelectronics is a half-bridge evaluation board designed to validate the STGAP2SiCD isolated dual gate driver for silicon carbide (SiC) MOSFETs. It supports high-voltage operation up to 1200 V, provides on-board isolated DC-DC converters (5.2 kV isolation), and enables configurable gate driving voltages (+17/0 V, +17/−3 V, +19/0 V, +19/−3 V) for optimized SiC switching performance in industrial motor drives.

For engineers reviewing the EVALSTGAP2SICD datasheet, EVALSTGAP2SICD pinout, EVALSTGAP2SICD application, or EVALSTGAP2SICD equivalent, this board delivers verified gate drive timing (75 ns propagation delay), 4 A source/sink capability, negative gate driving support, and integrated protection features including UVLO, thermal shutdown, interlocking, SD, and BRAKE pins - all critical for robust SiC power stage evaluation.

Technical Context

The board implements a galvanically isolated half-bridge gate drive architecture using the STGAP2SiCD IC in SO-36W package, with separate isolated power domains for high-side and low-side drivers supplied by Murata MGJ2D051509SC DC-DC converters. Logic-level inputs accept 3.3 V or 5 V TTL/CMOS signals with hysteresis, and dedicated SD/BRAKE pins enable fast fault response.

It supports TO-220 and TO-247 SiC MOSFETs up to 1700 V, includes jumper-selectable gate voltage configurations, and integrates Miller clamp (4 A), rail-to-rail outputs, and temperature shutdown. The design separates GNDISO_A/GNDISO_B domains to maintain isolation integrity during high dv/dt switching.

Key Specifications

Availability

EVALSTGAP2SICD is available at Aetrix Electronics and suitable for industrial motor drives, SiC-based EV charging systems, and renewable energy inverters requiring stable component supply and rapid prototyping validation of isolated gate drivers.

Supply support for EVALSTGAP2SICD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, MEMS, and microcontroller technologies for industrial, automotive, and consumer applications.

EVALSTGAP2SICD belongs to ST's high-voltage gate driver evaluation platform family, engineered specifically to accelerate development of SiC and GaN-based power converters with emphasis on isolation integrity, timing precision, and system-level protection integration.

FAQ

What power switches can be evaluated with EVALSTGAP2SICD?

The board supports N-channel SiC MOSFETs in TO-220 and TO-247 packages rated up to 1700 V, as confirmed by the bill of materials (Q1A/Q2A and Q1/Q2 references). It is not configured for IGBTs or silicon MOSFETs without rework, and no discrete power devices are included - users must supply compatible SiC switches.

Does EVALSTGAP2SICD provide isolated power for both high-side and low-side drivers?

Yes - two Murata MGJ2D051509SC isolated DC-DC converters supply independent 15 V rails to VH_A and VH_B, each with 5.2 kV DC isolation. These feed the high-side and low-side gate driver sections separately, maintaining galvanic separation required for reliable half-bridge operation.

How is negative gate voltage implemented on this board?

Negative gate driving (e.g., +17/−3 V) is achieved via on-board resistor networks and jumper configurations (JP3, JP6, JP9, JP11, JP13, JP15) that route clamped return paths through dedicated CLAMP_A/CLAMP_B pins of the STGAP2SiCD, enabling active Miller immunity during high dv/dt transitions.

Can the board be used without an external 5 V auxiliary supply?

No - VAUX = 5 V is mandatory to power the on-board isolated DC-DC converters and logic circuitry. The board lacks onboard AC-DC conversion or battery input; it requires a clean, regulated 5 V source connected via CN1/CN2/CN3 terminal blocks or J1/J2 headers.