STMicroelectronics EVSTGAP2GSN

Overview

EVSTGAP2GSN from STMicroelectronics is a half-bridge evaluation board designed to validate the STGAP2GSN isolated single gate driver and its operation with SGT120R65AL 650 V, 75 mΩ e-mode GaN transistors. It supports high-voltage rail up to 650 V, provides on-board isolated DC-DC converters (1.5 kV isolation), and enables negative gate driving (+6/−3 V configuration) for enhanced GaN switching control in industrial inverters.

For engineers reviewing the EVSTGAP2GSN datasheet, EVSTGAP2GSN pinout, EVSTGAP2GSN application, or EVSTGAP2GSN equivalent, this board serves as a validated platform for evaluating gate drive timing (45 ns propagation delay), dual-source/sink capability (2 A/3 A), UVLO optimized for GaN, thermal shutdown, and hardware interlock implementation using dual input pins.

Technical Context

The board implements two STGAP2GSN SO-8N gate drivers-one for high-side and one for low-side-each delivering rail-to-rail outputs, independent turn-on/turn-off optimization via external gate resistors, and TTL/CMOS-compatible inputs (3.3 V/5 V with hysteresis). The integrated dead-time generation circuit uses 74LVC1G86 XOR gates and Schmitt buffers to prevent cross-conduction.

Power delivery includes dual TBA 1-0512E isolated DC-DC converters supplying gate driver VH rails, with jumper-selectable logic supply (3.3 V or 5 V VAUX), and configurable gate drive voltage (±3 V or ±6 V). Functional isolation is rated at 1700 V, supporting safe evaluation of GaN-based power stages under realistic bus conditions.

Key Specifications

Availability

EVSTGAP2GSN is available at Aetrix Electronics and suitable for industrial motor drives, high-efficiency AC-DC power supplies, and GaN-based bidirectional DC-DC converters requiring stable component supply and rapid prototyping validation.

Supply support for EVSTGAP2GSN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, MEMS, and microcontroller technologies for industrial, automotive, and consumer applications.

The EVSTGAP2GSN belongs to ST's GaN ecosystem evaluation platform family, engineered to accelerate adoption of enhancement-mode GaN transistors by providing reference designs with validated gate drive, protection, and layout practices for high-frequency, high-efficiency power conversion.

FAQ

What is the maximum bus voltage supported by the EVSTGAP2GSN board?

The EVSTGAP2GSN board is rated for high-voltage rail operation up to 650 V DC, matching the breakdown voltage of the onboard SGT120R65AL GaN transistors. Its PCB layout, creepage/clearance distances, and gate driver isolation are validated for continuous operation at this level under industrial ambient conditions.

Can the EVSTGAP2GSN be used with silicon MOSFETs or IGBTs?

No-the EVSTGAP2GSN is specifically optimized for enhancement-mode GaN transistors, featuring UVLO thresholds, negative gate drive capability, and fast propagation delay tailored to GaN's zero-threshold and low-Qg characteristics. Using it with Si MOSFETs or IGBTs may result in improper biasing or insufficient drive strength due to mismatched timing and voltage requirements.

How is dead time generated and controlled on this board?

Dead time is implemented via discrete logic: dual 74LVC1G86 XOR gates and 74LVC1G17 Schmitt buffers generate complementary, non-overlapping PWM signals from a single input. Jumper-selectable HP/LP configuration allows default (HB=0/LB=1) or inverted (HB=1/LB=0) output polarity, enabling hardware-level interlock without controller firmware changes.

Does the board support external gate resistor adjustment?

Yes-each STGAP2GSN driver has dedicated GON and GOFF output pins routed to test points and solder pads (TP5, TP8, TP10, TP12), allowing direct insertion of external gate resistors to independently tune turn-on and turn-off slew rates. This supports fine-tuning of EMI, dV/dt stress, and switching losses in final system validation.