STMicroelectronics EVSTGAP2SICSAC

Overview

EVSTGAP2SICSAC from STMicroelectronics is a half-bridge evaluation board designed to validate the STGAP2SICSAC galvanically isolated single-channel SiC MOSFET gate driver. It supports up to 520 V DC bus voltage, integrates dual on-board 5.2 kV isolated DC-DC converters (MGJ2D051509SC), delivers ±4 A peak gate drive current, and enables configurable negative gate driving (+17/−3 V or +19/−3 V) for optimized SiC switching in motor inverters.

For engineers reviewing the EVSTGAP2SICSAC datasheet, EVSTGAP2SICSAC pinout, EVSTGAP2SICSAC application, or EVSTGAP2SICSAC equivalent, this board provides direct access to high-fidelity gate drive timing (45 ns propagation delay), Miller clamp functionality, UVLO tailored for SiC thresholds, thermal shutdown, and hardware interlock via dual input pins - all under real half-bridge switching conditions.

Technical Context

The board implements a functional half-bridge power stage using two SCT055H65G3AG 650 V / 58 mΩ SiC MOSFETs in H2PAK-7L packages, driven by two identical STGAP2SICSAC SO-8W isolated gate drivers. Each driver features rail-to-rail outputs, 4 A source/sink capability at 25 °C, and integrated Miller clamp to suppress dv/dt-induced gate spikes during high-speed commutation.

Power delivery includes isolated 15 V outputs (±15 V referenced to respective GNDISO) generated from a 5 V VAUX input via Murata MGJ2D051509SC converters, with 3.3 V logic supply derived either from VAUX or on-board regulation. Input logic accepts 3.3 V/5 V TTL/CMOS signals with hysteresis, and protection includes UVLO (optimized for SiC V_{GS(th)), thermal shutdown, and galvanic isolation rated at 6 kV.}

Key Specifications

Availability

EVSTGAP2SICSAC is available at Aetrix Electronics and suitable for industrial motor drives, SiC-based solar inverters, and EV onboard chargers requiring stable component supply, rapid prototyping validation, and gate driver performance benchmarking under realistic bus voltage and switching conditions.

Supply support for EVSTGAP2SICSAC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and sensor solutions for automotive, industrial, and consumer markets.

This board belongs to ST's SiC ecosystem enablement portfolio, developed specifically to accelerate adoption of silicon carbide technology in high-efficiency, high-voltage power conversion systems through validated reference designs and driver evaluation platforms.

FAQ

What power switches are mounted on the EVSTGAP2SICSAC board?

The board uses two SCT055H65G3AG 650 V, 58 mΩ, 30 A SiC MOSFETs in H2PAK-7L packages. These devices are AEC-Q100 qualified and optimized for high-frequency, high-efficiency operation with the STGAP2SICSAC driver's ±4 A output capability and Miller clamp function.

Can the EVSTGAP2SICSAC board operate with a 1200 V bus voltage?

Yes - the board's schematic and layout support 1200 V operation when the installed SCT055H65G3AG MOSFETs are replaced with higher-voltage-rated SiC devices (e.g., 1200 V parts in H2PACK-2L, H2PACK-7L, or HU3PAK packages) and C29 is upgraded to a 33 nF / 1.25 kV film capacitor as specified in the bill of materials.

How is isolated gate supply implemented on this board?

Two Murata MGJ2D051509SC isolated DC-DC converters generate ±15 V gate drive supplies from a single 5 V VAUX input. Each converter provides 5.2 kV isolation between primary (VAUX side) and secondary (gate drive side), powering high-side and low-side driver sections independently with dedicated GNDISO_H and GNDISO_L references.

Does the board support hardware interlock to prevent shoot-through?

Yes - the STGAP2SICSAC driver has dual independent input pins (IN+ and IN−) per channel, enabling hardware-based complementary signal injection with built-in interlock logic. This prevents cross-conduction during controller faults, and the board exposes both inputs for direct connection to external safety logic or FPGA-based dead-time controllers.