STMicroelectronics EVSTGAP2SICSANC

Overview

EVSTGAP2SICSANC from STMicroelectronics is a half-bridge evaluation board designed to validate the STGAP2SICSANC isolated single-channel gate driver for silicon carbide MOSFETs. It integrates two SCT055H65G3AG 650 V, 58 mΩ SiC MOSFETs in H2PAK-7L package, on-board 5.2 kV isolated DC-DC converters (MGJ2D051509SC), and configurable gate drive voltages (+17/0 V, +17/−3 V, +19/0 V, +19/−3 V), enabling evaluation of high-reliability SiC inverter stages up to 520 V bus voltage.

For engineers reviewing the EVSTGAP2SICSANC datasheet, EVSTGAP2SICSANC pinout, EVSTGAP2SICSANC application, or EVSTGAP2SICSANC equivalent, this board supports rapid validation of negative gate driving, Miller clamp behavior, UVLO thresholds optimized for SiC, thermal shutdown response, and propagation delay (45 ns) under real half-bridge switching conditions with 4 A source/sink capability.

Technical Context

The board implements a functional half-bridge power stage using dual STGAP2SICSANC SO-8 gate drivers - each delivering rail-to-rail 4 A peak output with integrated Miller clamp and 3.3 V/5 V TTL/CMOS-compatible inputs featuring hysteresis. The isolated DC-DC converters supply independent ±17 V or ±19 V gate bias to high-side and low-side drivers from a single 5 V VAUX input.

Hardware interlocking is enabled via dual independent input pins per driver, preventing cross-conduction during controller faults. UVLO thresholds are set specifically for SiC gate oxide integrity (e.g., ~12.5 V turn-on, ~9.5 V turn-off), and thermal shutdown activates at 150 °C with automatic recovery.

Key Specifications

Availability

EVSTGAP2SICSANC is available at Aetrix Electronics and suitable for industrial motor drives, SiC-based UPS systems, and renewable energy inverters requiring stable component supply, fast design iteration, and verified gate-drive performance under high dV/dt conditions.

Supply support for EVSTGAP2SICSANC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power devices, sensors, and analog ICs for automotive, industrial, and consumer applications.

The STGAP2SICSANC product line targets high-efficiency SiC-based power conversion, with this evaluation board engineered to accelerate adoption of wide-bandgap gate drivers in ruggedized industrial inverter designs.

FAQ

What power switches are mounted on the EVSTGAP2SICSANC board?

The board uses two SCT055H65G3AG silicon carbide MOSFETs - rated at 650 V, 58 mΩ typical R_DS(on), 30 A continuous current, and packaged in H2PAK-7L. These devices are AEC-Q100 qualified and optimized for high-frequency, high-efficiency switching in half-bridge configurations.

Can the EVSTGAP2SICSANC board operate with bus voltages above 520 V?

Yes - the board is rated for 520 V operation with its default SCT055H65G3AG MOSFETs, but supports higher bus voltages up to 1700 V when upgraded to compatible SiC devices in H2PACK-7L, H2PACK-2L, or HU3PAK packages, along with appropriate re-rating of C29 (33 nF/1.25 kV film capacitor) and other HV decoupling elements.

How is negative gate voltage generated and controlled on this board?

Negative gate voltage is generated by the on-board Murata MGJ2D051509SC isolated DC-DC converters, which produce independent ±17 V or ±19 V rails. Jumper configuration (JP2, JP8, etc.) selects between +17/0 V, +17/−3 V, +19/0 V, and +19/−3 V drive schemes - enabling precise control of SiC turn-off dynamics and shoot-through immunity.

Does the board support hardware interlock for high-side and low-side drivers?

Yes - each STGAP2SICSANC driver has dedicated IN+ and IN− pins, allowing implementation of hardware interlocking logic. This prevents simultaneous conduction during controller failure by ensuring complementary signals are enforced at the gate driver level, independent of MCU firmware behavior.