STMicroelectronics EVSTGAP2SICSN

Overview

EVSTGAP2SICSN from STMicroelectronics is a half-bridge evaluation board designed to validate the STGAP2SICSN isolated 4 A single gate driver for SiC MOSFETs, supporting up to 520 V DC bus voltage, featuring on-board isolated DC-DC converters (5.2 kV isolation), negative gate driving capability (+17/−3 V configuration), and dual independent source/sink outputs for optimized SiC switching in industrial motor drives.

For engineers reviewing the EVSTGAP2SICSN datasheet, EVSTGAP2SICSN pinout, EVSTGAP2SICSN application, or EVSTGAP2SICSN equivalent, this board enables rapid validation of high-voltage SiC gate drive performance-including propagation delay (75 ns), UVLO thresholds, thermal shutdown behavior, and jumper-selectable driving voltages-under real half-bridge conditions with accessible test points and modifiable components.

Technical Context

The board implements two STGAP2SICSN SO-8 gate drivers-one per switch-with separate high-side and low-side isolated power supplies generated by Murata MGJ2D051509SC DC-DC converters (5 V input → +15 V/−9 V output). Each driver provides rail-to-rail 4 A peak source/sink current and supports TTL/CMOS 3.3 V or 5 V inputs with hysteresis.

It integrates functional 1700 V isolation between control and power domains, uses SCTH35N65G2V-7 SiC MOSFETs (650 V, 55 mΩ) in H2PAK-7 package, and enables independent turn-on/turn-off tuning via dedicated gate resistors (R1/R6 = 12 Ω, R2/R8 = 2.2 Ω), while supporting hardware interlock through dual IN+/IN− inputs per channel.

Key Specifications

Availability

EVSTGAP2SICSN is available at Aetrix Electronics and suitable for industrial motor drives, SiC inverter development, and high-efficiency power conversion systems requiring stable component supply and fast-turnaround evaluation platforms.

Supply support for EVSTGAP2SICSN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power devices, sensors, and analog ICs for industrial, automotive, and consumer applications.

This board belongs to ST's SiC ecosystem evaluation platform series, developed specifically to accelerate adoption of silicon carbide technology in high-voltage, high-frequency motor control and renewable energy inverters.

FAQ

What power switches are mounted on the EVSTGAP2SICSN board?

The board ships with two SCTH35N65G2V-7 SiC MOSFETs in H2PAK-7 package-650 V rated, 55 mΩ R_DS(on), 45 A continuous current-configured as a half-bridge. These are pre-soldered and electrically optimized for evaluation with the STGAP2SICSN driver's negative gate drive capability and 4 A peak output.

Can the EVSTGAP2SICSN operate with a 3.3 V logic supply only?

Yes-the board accepts either VAUX = 5 V or the internally regulated 3.3 V (generated by U3/U4 DC-DC converters) to power VDD logic rails. The STGAP2SICSN drivers support 3.3 V TTL/CMOS inputs with hysteresis, and all jumpers and test points are configured for direct 3.3 V controller interfacing without level shifting.

How is high-side gate power supplied on this board?

High-side gate power is delivered by an on-board Murata MGJ2D051509SC isolated DC-DC converter (U3), which takes VAUX = 5 V input and generates +15 V/−9 V outputs. This provides the required floating bias for the high-side STGAP2SICSN driver's VH pin and enables true negative gate driving (e.g., +17 V/−3 V) without external bias supplies.

Does the board support hardware interlock to prevent shoot-through?

Yes-each STGAP2SICSN channel has dual differential inputs (IN+ and IN−), allowing hardware-based interlock implementation. When one channel's IN+ is asserted, the complementary IN− of the other channel can be tied to force inactive state, physically preventing simultaneous conduction even during MCU fault or timing error.