Texas Instruments F28M35H52C1RFPQ

Overview

F28M35H52C1RFPQ from Texas Instruments is a dual-core Concerto™ microcontroller integrating an Arm® Cortex®-M3 master subsystem (100 MHz) and a TMS320C28x real-time control subsystem (150 MHz), with 512KB ECC flash, 32KB RAM (ECC/parity), 64KB shared RAM, dual 12-bit ADCs (2.88 MSPS, 20 channels), six comparators with integrated DACs, and dual CAN, USB OTG + PHY, 10/100 ENET 1588, and ePWM/eCAP/eQEP peripherals - deployed in solar string inverters and industrial AC drive control modules.

For engineers reviewing the F28M35H52C1RFPQ datasheet, F28M35H52C1RFPQ pinout, F28M35H52C1RFPQ application, or F28M35H52C1RFPQ equivalent, key selection criteria include dual-core clock coordination (100/150 MHz), AEC-Q100 qualified Q-grade thermal rating (–40°C to 125°C free-air), HTQFP-144 PowerPAD™ package with exposed thermal pad, IPC message RAM for interprocessor synchronization, and hardware safety features including ECC, parity, and dual security zones.

Technical Context

The F28M35H52C1RFPQ implements a tightly coupled dual-subsystem architecture: the Cortex-M3 handles high-level communication (Ethernet 1588, USB OTG, dual CAN, five UARTs) while the C28x executes deterministic real-time control (nine ePWM modules with 16 high-resolution outputs, six eCAP, three eQEP, VCU-accelerated math). Clock domains are independently configurable via dynamic PLL ratio changes, with integer-divide constraints linking C28x and ADC timing.

Shared resources include 64KB parity-protected RAM, dual 12-bit ADCs with four S/H circuits and independent reference inputs, six analog comparators each paired with a 10-bit DAC, and a single EPI arbitrated between both cores. Safety is enforced through ECC on flash and L1/L0 RAM, parity on L2/L3/C3/C2 RAM, NMI watchdogs per subsystem, and critical register lock protection.

Key Specifications

Pinout & Package

Package: 144-pin RFP PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP), 20.0 mm × 20.0 mm body size, with exposed thermal pad requiring soldering to PCB ground plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core real-time control applications.

Compared with F28M35H52C-Q1, the F28M35H52C1RFPQ offers identical silicon functionality but targets industrial and non-automotive applications where AEC-Q100 certification is not required; versus TMS320F28388D, it trades single-core performance and EtherCAT for true hardware-isolated dual-CPU operation and integrated USB/Ethernet 1588 - making it optimal for self-contained smart inverters and distributed control nodes.

Availability

F28M35H52C1RFPQ is available at Aetrix Electronics and suitable for solar string inverters, industrial servo drives, and automotive onboard chargers requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-aligned thermal reliability.

Supply support for F28M35H52C1RFPQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies with leadership in industrial, automotive, and power management markets.

The F28M35H52C1RFPQ belongs to TI's Concerto™ family - designed specifically to unify high-bandwidth communication and deterministic real-time control in a single chip for energy conversion, motor control, and smart grid applications.

FAQ

What is the maximum operating frequency of each core in the F28M35H52C1RFPQ?

The F28M35H52C1RFPQ features an Arm Cortex-M3 core rated up to 100 MHz and a TMS320C28x core rated up to 150 MHz. These frequencies are achievable simultaneously under specific clock divider configurations; however, integer-divide constraints between the two PLL domains mean that full 100/150 MHz operation requires careful clock tree design per Section 8.10 of the SPRS742L datasheet. The F28M35H52C1RFPQ datasheet confirms this dual-speed capability is implemented in silicon.

Does the F28M35H52C1RFPQ support AEC-Q100 qualification?

Yes, the F28M35H52C1RFPQ is AEC-Q100 qualified for automotive applications, indicated by its "Q" suffix and specification of –40°C to 125°C free-air operating temperature. This qualification covers stress testing for temperature cycling, humidity, and ESD per AEC-Q100 Rev-H, and is documented in TI's official device folder and SPRS742L revision history. The F28M35H52C1RFPQ meets Grade 1 requirements for automotive use cases such as onboard chargers and battery management gateways.

How many high-resolution PWM outputs does the F28M35H52C1RFPQ provide?

The F28M35H52C1RFPQ provides 16 high-resolution PWM (HRPWM) outputs across its nine ePWM modules. Each ePWM module supports dual outputs (A/B), and 16 of the 18 total outputs are enhanced with high-resolution capability enabling 150-ps duty-cycle adjustment - essential for precise dead-time control in SiC/GaN-based power stages. This specification is explicitly listed in Table 5-1 of the F28M35H52C1RFPQ datasheet under "High-Resolution PWM (HRPWM) outputs".

What analog-to-digital converter performance does the F28M35H52C1RFPQ deliver?

The F28M35H52C1RFPQ integrates two independent 12-bit ADCs, each capable of 2.88 MSPS sampling rate with 347 ns conversion time and up to 10 input channels. Combined, they support 20 total analog inputs with four shared sample-and-hold circuits. Both ADCs feature separate reference inputs (VREFHI/VREFLO) and operate with programmable acquisition windows - enabling synchronized sampling of current, voltage, and temperature in motor control applications. This performance is confirmed in Section 7.10 and Table 5-1 of the F28M35H52C1RFPQ datasheet.

What is the purpose of the IPC Message RAM in the F28M35H52C1RFPQ?

The F28M35H52C1RFPQ includes 2KB of dedicated IPC Message RAM (1KB CTOM + 1KB MToc) used exclusively for low-latency, lock-free data exchange between the Cortex-M3 and C28x subsystems. It operates alongside 32 hardware handshaking channels - 4 of which generate interrupts - allowing deterministic synchronization without software polling. This architecture enables real-time coordination of control tasks (e.g., C28x PWM updates triggered by Cortex-M3 network commands), as detailed in Sections 8.3 and 8.4 of the F28M35H52C1RFPQ technical reference.