Texas Instruments F28M36H33C2ZWTS

Overview

F28M36H33C2ZWTS from Texas Instruments is a dual-core Concerto™ microcontroller integrating an Arm® Cortex®-M3 master subsystem (100 MHz) and a TMS320C28x real-time control subsystem (150 MHz), with dual 12-bit ADCs (2.88 MSPS, 24 channels), 12 ePWM modules (24 outputs, 16 high-resolution), and 6 comparators with integrated 10-bit DACs - deployed in industrial motor drives and solar inverters.

For engineers reviewing the F28M36H33C2ZWTS datasheet, F28M36H33C2ZWTS pinout, F28M36H33C2ZWTS application, or F28M36H33C2ZWTS equivalent, key selection criteria include dual-core clock coordination (Cortex-M3 @ 100 MHz / C28x @ 150 MHz), shared 64KB parity RAM, ZWT nFBGA-289 package compatibility, and absence of Ethernet/USB peripherals versus P-series variants.

Technical Context

The F28M36H33C2ZWTS implements tightly coupled interprocessor communication via 32-channel IPC with 2KB message RAM per subsystem and hardware handshaking - enabling deterministic data exchange between Cortex-M3 and C28x without bus arbitration overhead. Its analog subsystem features two independent 12-bit ADCs with synchronized sampling across 24 total channels and four sample-and-hold circuits.

Clocking uses dual PLLs: one for the Cortex-M3 domain (100 MHz max) and one for the C28x domain (150 MHz max), with mandatory integer divide ratio maintenance between cores. Safety architecture includes ECC on flash (512KB C28x / 512KB M3), parity on RAM blocks, and dual security zones (128-bit password each) for code protection.

Key Specifications

Pinout & Package

289-ball ZWT New Fine Pitch Ball Grid Array (nFBGA), 16.0 mm × 16.0 mm body size, 0.8 mm ball pitch, RoHS-compliant, lead-free finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core real-time control applications.

Compared with F28M36P53C2ZWTS, the F28M36H33C2ZWTS omits Ethernet/USB to reduce cost and complexity while retaining full analog/peripheral capability for cost-sensitive inverters; versus TMS320F28388D, it trades dual-C28x determinism for Arm-based protocol flexibility and lower BOM count.

Availability

F28M36H33C2ZWTS is available at Aetrix Electronics and suitable for industrial motor drives, solar string inverters, three-phase UPS systems, and AC-input BLDC motor drives requiring stable component supply across extended product lifecycles.

Supply support for F28M36H33C2ZWTS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of leadership in industrial and automotive microcontrollers.

The F28M36x Concerto™ family was designed to unify communication and real-time control in single-chip solutions for solar, motor, and power conversion systems - bridging the gap between protocol-aware connectivity and nanosecond-precision control.

FAQ

What is the maximum operating frequency of each core in the F28M36H33C2ZWTS?

The F28M36H33C2ZWTS operates its Arm Cortex-M3 core at up to 100 MHz and its TMS320C28x core at up to 150 MHz. These frequencies are fixed per device variant - unlike the P63C2, the H33C2 does not support 125 MHz Cortex-M3 operation. The clock divider constraints ensure integer ratios between domains, preserving timing integrity across subsystems. This configuration is confirmed in Table 3-1 of SPRS825F.

Does the F28M36H33C2ZWTS include Ethernet or USB peripherals?

No, the F28M36H33C2ZWTS excludes both 10/100 ENET 1588 MII and USB OTG + PHY peripherals. This distinguishes it from the P-series variants (e.g., F28M36P53C2ZWTS) and is explicitly documented in Table 3-1 of the SPRS825F datasheet under "10/100 ENET 1588 MII" and "USB OTG FS" rows, where H33B2/H33C2 entries show "No".

How much shared RAM does the F28M36H33C2ZWTS provide, and what is its protection scheme?

The F28M36H33C2ZWTS provides 64KB of shared RAM implemented with parity error detection. This memory is accessible by both the Cortex-M3 and C28x subsystems and is mapped into both address spaces. Parity checking occurs on every read/write access, triggering interrupts on detected errors - a key safety feature for industrial applications requiring IEC 61508 compliance.

What analog peripherals are integrated into the F28M36H33C2ZWTS?

The F28M36H33C2ZWTS integrates dual independent 12-bit ADCs (ADC1 and ADC2), each supporting up to 12 input channels (24 total), 2.88 MSPS aggregate sampling rate, and four sample-and-hold circuits. It also includes six analog comparators, each with an integrated 10-bit DAC for programmable threshold generation - all documented in Section 1.1 and Table 3-1 of SPRS825F.

Is the F28M36H33C2ZWTS pin-compatible with other F28M36x devices in the ZWT package?

Yes, the F28M36H33C2ZWTS is pin-compatible with all F28M36x devices in the 289-ball ZWT nFBGA package, including F28M36P63C2ZWTS and F28M36P53C2ZWTS. Pin assignments, ball grid layout, and mechanical footprint are identical across the family - verified in Figure 4-1 through Figure 4-5 and Table 4-1 of SPRS825F.