Texas Instruments F28M36H53B2ZWTT

Overview

F28M36H53B2ZWTT from Texas Instruments is a dual-core Concerto™ microcontroller integrating an Arm® Cortex®-M3 master subsystem (100 MHz) and a TMS320C28x real-time control subsystem (150 MHz), with dual 12-bit ADCs (2.88 MSPS, 24 total channels), 12 ePWM modules (24 outputs, 16 high-resolution), 6 comparators with integrated 10-bit DACs, and 289-ball nFBGA packaging. It targets industrial motor drives and power conversion systems requiring concurrent communication and deterministic control.

For engineers reviewing the F28M36H53B2ZWTT datasheet, F28M36H53B2ZWTT pinout, F28M36H53B2ZWTT application, or F28M36H53B2ZWTT equivalent, key selection criteria include its 100/150 MHz dual-core speed pairing, absence of Ethernet and USB-OTG (vs. P-series), 512KB C28x flash + 512KB M3 flash, shared 64KB RAM, and ZWT package thermal performance at –40°C to 105°C junction temperature.

Technical Context

The F28M36H53B2ZWTT implements strict hardware separation between its Cortex-M3 communications subsystem and C28x real-time control subsystem, coordinated via 32-channel IPC with 2KB message RAM and handshaking interrupts. Clocking uses independent PLLs with dynamic ratio changes, supporting validated core speed combinations: 100 MHz M3 / 100 MHz C28x or 75 MHz M3 / 150 MHz C28x.

Analog resources are shared: dual synchronized 12-bit ADCs operate up to 2.88 MSPS with 347 ns conversion time and four S/H circuits; six analog comparators each integrate a 10-bit DAC for fast trip-zone generation, directly feeding ePWM fault protection logic without CPU intervention.

Key Specifications

Pinout & Package

289-ball New Fine Pitch Ball Grid Array (nFBGA), 16.0 mm × 16.0 mm body size, 0.8 mm ball pitch, RoHS-compliant, designed for automated surface-mount assembly and thermal management in industrial power modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core real-time control applications.

Compared with F28M36P53C2ZWTT, the F28M36H53B2ZWTT trades Ethernet/USB for lower cost and power in cost-sensitive inverters; versus TMS320F28388D, it offers Arm-based protocol offload but less analog channel density and no EtherCAT - making it optimal for mid-tier solar and motor drives where balanced communication/control integration is critical.

Availability

F28M36H53B2ZWTT is available at Aetrix Electronics and suitable for AC drive control modules, servo drive control modules, string inverters, and central inverters requiring stable component supply across extended production lifecycles.

Supply support for F28M36H53B2ZWTT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and digital signal processing technologies for industrial, automotive, and communications markets.

The F28M36x Concerto™ family was designed to unify high-speed communication and deterministic real-time control on a single chip, targeting solar inverters, industrial motor drives, and UPS systems requiring functional safety and multi-protocol connectivity.

FAQ

What distinguishes F28M36H53B2ZWTT from the P-series Concerto devices like F28M36P53C2ZWTT?

The F28M36H53B2ZWTT omits Ethernet 1588 and USB-OTG peripherals present in P-series variants, resulting in lower cost and power consumption. Its Cortex-M3 operates at 100 MHz (vs. 125 MHz in P63/P53), and it lacks the 10/100 ENET MII interface and USB PHY. This makes F28M36H53B2ZWTT ideal for cost-sensitive, non-Ethernet solar and motor drive applications where those interfaces are handled externally. All other core features - dual 12-bit ADCs, 12 ePWM modules, IPC, and memory - remain identical in F28M36H53B2ZWTT.

Does F28M36H53B2ZWTT support functional safety certification for industrial applications?

Yes, F28M36H53B2ZWTT includes hardware features aligned with IEC 61508 SIL-2 requirements: ECC-protected flash (512KB C28x, 512KB M3), parity-protected RAM (112KB M3, 16KB C28x, 64KB shared), dual watchdog timers, NMI watchdog for both cores, and critical register lock protection. Texas Instruments provides safety documentation including FMEDA reports and diagnostic software libraries specifically validated for F28M36H53B2ZWTT, enabling certified system-level safety architecture design.

What is the maximum achievable ADC sampling rate and channel count for simultaneous acquisition on F28M36H53B2ZWTT?

F28M36H53B2ZWTT supports simultaneous sampling across all 24 ADC input channels (12 per ADC module) at a combined rate of 2.88 MSPS, with 347 ns conversion time per channel. Both ADC1 and ADC2 are hardware-synchronized, allowing true simultaneous capture of motor phase currents and voltages - essential for accurate field-oriented control. The 24 channels are distributed across two independent 12-channel banks, each with its own S/H circuitry and configurable trigger sources.

Can F28M36H53B2ZWTT generate high-resolution PWM signals for SiC or GaN transistor gate drivers?

Yes, F28M36H53B2ZWTT's 12 ePWM modules deliver 16 high-resolution PWM (HRPWM) outputs with 150-ps step resolution, enabling precise dead-time control and carrier-based modulation required for wide-bandgap transistors. Each HRPWM channel supports independent frequency, duty cycle, and phase adjustment, and integrates trip-zone logic directly tied to the 6 analog comparators - allowing sub-100 ns overcurrent shutdown without CPU involvement, critical for protecting expensive SiC/GaN switches.

How does interprocessor communication (IPC) work between the Cortex-M3 and C28x subsystems in F28M36H53B2ZWTT?

F28M36H53B2ZWTT implements a hardware-accelerated 32-channel IPC mechanism with dedicated handshaking logic and two 2KB message RAM blocks (CTOM and MToc). Channels can generate interrupts on either core, enabling event-driven coordination - for example, the C28x core writes ADC results to shared RAM and triggers an IPC interrupt to notify the Cortex-M3 that new sensor data is ready for protocol processing. This eliminates polling, reduces latency to <500 ns, and ensures deterministic real-time behavior in F28M36H53B2ZWTT-based systems.