Texas Instruments F28M36H53C2ZWTS

Overview

F28M36H53C2ZWTS from Texas Instruments is a dual-core Concerto™ microcontroller integrating an Arm® Cortex®-M3 (100 MHz) and TMS320C28x (150 MHz) real-time control CPU on a single die, with dual 12-bit ADCs (2.88 MSPS), 12 ePWM modules (24 outputs), 6 comparators with integrated DACs, and 142 GPIOs. It targets high-precision industrial motor drives and power conversion systems requiring concurrent communication and deterministic control.

For engineers reviewing the F28M36H53C2ZWTS datasheet, F28M36H53C2ZWTS pinout, F28M36H53C2ZWTS application, or F28M36H53C2ZWTS equivalent, key selection criteria include dual-core clock coordination (100/150 MHz), shared 64KB parity RAM, nFBGA-289 package compatibility, and safety features including ECC flash, dual watchdogs, and IPC message RAM for interprocessor synchronization.

Technical Context

The F28M36H53C2ZWTS implements a tightly coupled dual-subsystem architecture: the Master Subsystem (Cortex-M3) handles Ethernet 1588, USB OTG + PHY, dual CAN, 5 UARTs, and 4 SSIs for connectivity; the Control Subsystem (C28x) executes real-time PWM generation, encoder capture, and floating-point math via its FPU and VCU accelerator. Both subsystems share analog resources, EPI, and IPC infrastructure.

Clocking is managed through independent PLLs with dynamic ratio changes supported; the C28x core runs at 150 MHz while the Cortex-M3 operates at 100 MHz - a validated speed combination per TI's device comparison table. Safety is enforced via ECC on 512KB C28x flash and 512KB M3 flash, parity on RAM blocks, and dual security zones (128-bit password per zone).

Key Specifications

Pinout & Package

Package: 289-ball ZWT New Fine Pitch Ball Grid Array (nFBGA), 16.0 mm × 16.0 mm body size, 0.8 mm ball pitch, RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core real-time control applications.

Compared with F28M36H53C2ZWTS, F28M36P53C2ZWTS offers higher M3 clock speed and Ethernet, while TMS320F28388D trades Arm connectivity for deeper C28x control acceleration - making F28M36H53C2ZWTS optimal for balanced communication+control workloads in power electronics.

Availability

F28M36H53C2ZWTS is available at Aetrix Electronics and suitable for industrial motor drives, solar inverters, and uninterruptible power supplies requiring stable component supply across extended product lifecycles.

Supply support for F28M36H53C2ZWTS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in industrial, automotive, and power management solutions.

The F28M36x Concerto™ family was designed to unify communication and real-time control in a single chip - targeting solar inverters, motor drives, and industrial automation systems needing both high-level protocol handling and sub-microsecond deterministic response.

FAQ

What is the maximum operating junction temperature for F28M36H53C2ZWTS?

The F28M36H53C2ZWTS is rated for –40°C to 125°C junction temperature (S-grade), verified in TI's SPRS825F datasheet Section 1.1 and Table 3-1. This rating applies to continuous operation under specified thermal conditions with appropriate PCB copper area and airflow. The 'S' suffix in F28M36H53C2ZWTS explicitly denotes the 125°C capability, distinguishing it from the 105°C 'T' variant.

Does F28M36H53C2ZWTS support pin-compatible replacement with other F28M36x devices?

No, F28M36H53C2ZWTS is not pin-compatible with P-series variants like F28M36P63C2ZWTS due to differences in peripheral enablement - specifically, the H53C2 lacks Ethernet 1588 and USB OTG hardware blocks present in P63C2. Pin assignments match within the H53x family (e.g., F28M36H53B2), but signal functionality may differ based on silicon revision and configuration fuses.

How does the IPC mechanism work between the Cortex-M3 and C28x cores in F28M36H53C2ZWTS?

F28M36H53C2ZWTS uses a 32-channel hardware IPC with dedicated handshaking logic and two 2KB message RAM blocks (one per core). Each channel supports interrupt generation and memory-mapped access, enabling zero-copy data transfer. The IPC is documented in Sections 6.3 and 6.4 of SPRS825F and requires explicit initialization of mailbox registers and interrupt vectors in both subsystems' firmware.

What analog peripherals are shared between the two cores in F28M36H53C2ZWTS?

In F28M36H53C2ZWTS, both the dual 12-bit ADCs (ADC1 and ADC2), six comparators with integrated 10-bit DACs, and four sample-and-hold circuits are accessible to both the Cortex-M3 and C28x subsystems via the Analog Common Interface Bus. Resource arbitration is handled in hardware, with priority given to the C28x for time-critical sampling - confirmed in Section 6.5 of SPRS825F.

Can F28M36H53C2ZWTS execute code from external memory via the EPI interface?

Yes, F28M36H53C2ZWTS supports external memory expansion through its External Peripheral Interface (EPI), which is arbitrated between the Cortex-M3 and C28x masters. The EPI supports SRAM, NOR flash, and FPGA interfaces with programmable wait states and burst modes. However, only the C28x subsystem can access EPI memory above 2 MB - a limitation noted in Table 6-7 of SPRS825F.