Texas Instruments F28P650SH7ZEJR
- Part No.:
- F28P650SH7ZEJR
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- 256-LFBGA
- Datasheet:
-
F28P650SH7ZEJR.pdf
- Description:
- C2000 32-bit MCU, 400 MIPS
- Quantity:
- Payment:

- Shipping:

Inventory:1,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
F28P650SH7ZEJR from Texas Instruments is a C2000™ real-time microcontroller featuring one 32-bit C28x DSP CPU and one CLA CPU, both operating at 200 MHz, 1.28 MB ECC-protected flash, 248 KB parity-protected RAM, and triple 16-bit/12-bit ADCs (1.19 MSPS @ 16-bit). It delivers 400 MIPS total processing power for high-fidelity motor control in industrial servo drives and solar string inverters.
For engineers reviewing the F28P650SH7ZEJR datasheet, F28P650SH7ZEJR pinout, F28P650SH7ZEJR application, or F28P650SH7ZEJR equivalent, key selection criteria include EtherCAT® SubDevice support, dual CAN FD interfaces, 36-channel HRPWM with 150 ps resolution, CLB-configurable logic, and ASIL B/SIL 2 functional safety certification - all in a 169-ball nFBGA (NMR) package.
Technical Context
The F28P650SH7ZEJR implements a single-CPU C28x + CLA architecture optimized for deterministic real-time control loops. Its analog subsystem integrates three independent ADCs with hardware oversampling (up to 128×), simultaneous sampling via dedicated S/H, and automatic result comparison for functional safety.
Control peripherals include 36 ePWM channels with Minimum Dead-Band Logic (MINDB) and Illegal Combo Logic (ICL), seven eCAP modules (two with HRCAP), six eQEP units, and a Configurable Logic Block (CLB) with six logic tiles - enabling FPGA-like peripheral augmentation without external components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Configuration | One C28x DSP core + one CLA CPU, both at 200 MHz - enables parallel real-time control law execution without CPU contention. |
| Flash / RAM | 1.28 MB ECC-protected flash (5 banks); 248 KB enhanced parity RAM - supports robust firmware storage and runtime data integrity in harsh environments. |
| ADC Performance | Three 16-bit/12-bit ADCs: 1.19 MSPS @ 16-bit or 3.92 MSPS @ 12-bit, with 40 SE/19 DIFF inputs - enables high-resolution current/voltage sensing across multi-phase power stages. |
| PWM Capability | 36 ePWM channels, all with 150 ps high-resolution timing - supports GaN/SiC gate driving in resonant, multilevel, and matrix converters. |
| Safety Certification | ISO 26262 ASIL B (TÜV SÜD) and IEC 61508 SIL 2 certified - provides documented hardware integrity and systematic capability for functional safety system integration. |
| Communication Interfaces | Dual CAN FD, EtherCAT® SubDevice Controller, USB 2.0, FSI (200 Mbps), 4× SPI, 2× UART, 2× I²C, PMBus - enables deterministic fieldbus connectivity and isolated high-speed diagnostics. |
| Package | 169-ball nFBGA (NMR), 9 mm × 9 mm, 0.65 mm pitch - compact thermally efficient footprint suitable for space-constrained motor control modules. |
Pinout & Package
Package: 169-ball New Fine Pitch Ball Grid Array (nFBGA), 9 mm × 9 mm, 0.65 mm pitch, lead-free/green compliant. Thermal pad on underside for enhanced heat dissipation in high-power-density applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDA / VSSA | Analog Power / Ground | Separate 3.3 V analog supply and ground planes isolate noise-sensitive ADC/DAC operation from digital switching transients. |
| A0/DACA_OUT | Analog Output | First buffered 12-bit DAC output for slope-compensated peak/valley current mode control reference generation. |
| B0/VDAC | Analog Output | Second buffered 12-bit DAC output supporting independent reference or calibration signal generation. |
| A9–A15, B1–B13, C1–C13 | GPIO / Peripheral Multiplex | 119 general-purpose I/O pins with configurable pull-up/down, supporting ADC input, PWM, eCAP, eQEP, and CLB interconnect functions. |
| VREFHIA / VREFLOA | ADC Reference | Independent high/low analog reference inputs per ADC block - enable differential measurement flexibility and ratiometric sensor interfacing. |
Key Features
| Feature | Design Value |
|---|---|
| Control Law Accelerator (CLA) | Independent 200 MHz single-precision floating-point CPU offloads time-critical control loops from main C28x, reducing jitter and latency in closed-loop response. |
| Configurable Logic Block (CLB) | Six programmable logic tiles implement custom encoder interfaces, PWM edge shaping, or fault logic - eliminating need for external CPLD/FPGA in power stage control. |
| Hardware ADC Redundancy Checker | Automatically compares conversion results across multiple ADC modules for consistency - enables functional safety compliance without software overhead or CPU cycle penalty. |
| EtherCAT® SubDevice Controller | Integrated ESC eliminates external ASIC for real-time industrial Ethernet slave node implementation - reduces BOM cost and PCB area in servo drive and motion controller designs. |
| Live Firmware Update (LFU) | Hardware-assisted context switching allows seamless transition between old and new firmware images - supports zero-downtime field updates in mission-critical power systems. |
Applications
| Servo Drive Control Module | Solar String Inverter |
|---|---|
Use Scenario: High-bandwidth position and torque control in industrial robotic arms using dual-axis servo amplifiers. IC Role / Device Role / Timing Role: Real-time motor control MCU executing field-oriented control (FOC) and space-vector modulation (SVM) at 20 kHz loop rate with sub-microsecond PWM update. Use Value: 36-channel HRPWM with MINDB/ICL ensures precise dead-time management for SiC half-bridges, minimizing shoot-through risk while maximizing efficiency. |
Use Scenario: Distributed DC-to-AC conversion in rooftop PV arrays with module-level MPPT and grid-synchronization. IC Role / Device Role / Timing Role: Central controller managing interleaved boost stages, DC-link regulation, and grid-tie inverter modulation with harmonic suppression. Use Value: Triple ADC with hardware oversampling and outlier rejection enables accurate current sensing across multiple strings under partial shading conditions. |
| Industrial HVAC Motor Control | DC Fast Charging Station |
Use Scenario: Variable-speed compressor and fan control in large commercial HVAC systems requiring energy optimization and acoustic noise reduction. IC Role / Device Role / Timing Role: Real-time thermal-aware motor control unit implementing sensorless FOC and adaptive voltage feedforward compensation. Use Value: CLB-configured logic implements custom commutation sequencing for permanent magnet motors - eliminating external gate driver logic ICs. |
Use Scenario: Bidirectional AC/DC and DC/DC power conversion in 150–350 kW EV charging stations with dynamic load balancing and grid-support functions. IC Role / Device Role / Timing Role: Master controller coordinating multiple parallel power modules, managing isolation communication via FSI, and enforcing safety shutdown protocols. Use Value: Dual CAN FD interfaces enable high-speed coordination between rectifier, DC-link, and inverter modules while maintaining functional safety separation boundaries. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar real-time motor control applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TMS320F28P650DK9ZEJ | Two C28x CPUs + CLA, 256-ball ZEJ package (13 mm × 13 mm), EtherCAT® enabled, lockstep support. | Targeted at higher-integrity applications requiring dual-core redundancy and larger I/O count (185 GPIO). | Select when dual-CPU lockstep, EtherCAT®, or expanded analog/peripheral resources are required - not drop-in compatible due to package and pinout differences. |
| TMS320F28377DPTP | Dual C28x + dual CLA, 176-pin HLQFP, 1 MB flash, no EtherCAT®, no CAN FD, lower safety certification level. | Designed for cost-sensitive industrial drives where ASIL B certification and advanced fieldbus are not mandatory. | Choose for legacy C2000 migration paths with existing PTP footprint - requires PCB redesign and firmware adaptation due to peripheral and safety feature gaps. |
Compared with F28P650SH7ZEJR, the DK9ZEJ offers higher functional safety assurance and EtherCAT® integration but demands larger board area and layout changes, while the F28377DPTP provides dual-core compute at lower cost but lacks ASIL B certification, CAN FD, and hardware safety accelerators critical for next-gen EV and solar infrastructure.
Availability
F28P650SH7ZEJR is available at Aetrix Electronics and suitable for industrial servo drives, solar string inverters, and DC fast charging stations requiring stable component supply, long-term lifecycle support, and traceable sourcing for automotive-qualified production programs.
Supply support for F28P650SH7ZEJR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 50 years of innovation in power electronics and real-time control systems.
The F28P650SH7ZEJR belongs to TI's C2000™ real-time MCU product line, engineered specifically for ultra-low-latency, high-precision control in power conversion, motor drives, and renewable energy systems - emphasizing silicon-level determinism, integrated safety, and fieldbus readiness.
FAQ
What is the core architecture of the F28P650SH7ZEJR?
The F28P650SH7ZEJR features a single 32-bit C28x DSP CPU and one Control Law Accelerator (CLA) CPU, both running at 200 MHz. It does not include a second C28x CPU or lockstep configuration. This architecture balances high-performance real-time control with reduced complexity and cost for mid-tier motor and power applications.
Does F28P650SH7ZEJR support EtherCAT® functionality?
No, F28P650SH7ZEJR does not include an EtherCAT® SubDevice Controller. EtherCAT® is only available on select variants such as F28P650DK9ZEJ and F28P650DK7ZEJ. The F28P650SH7ZEJR retains dual CAN FD, USB 2.0, FSI, and multiple serial interfaces for alternative industrial networking.
What package type and pin count does F28P650SH7ZEJR use?
F28P650SH7ZEJR uses a 169-ball New Fine Pitch Ball Grid Array (nFBGA) package with NMR suffix, measuring 9 mm × 9 mm and 0.65 mm ball pitch. It provides 119 GPIO pins (excluding JTAG/X1/X2), 22 AGPIO pins shared with ADC inputs, and dedicated analog power/ground balls for noise-sensitive operation.
Is F28P650SH7ZEJR qualified for automotive applications?
No, F28P650SH7ZEJR is an industrial-grade device rated for –40°C to 125°C ambient temperature. Automotive-qualified equivalents include the F28P659SH6-Q1 (AEC-Q100 Grade 1), which shares the same NMR package but adds automotive-specific qualification, enhanced ESD ratings, and different flash/RAM configurations.
What safety certifications apply to F28P650SH7ZEJR?
F28P650SH7ZEJR is ISO 26262 certified up to ASIL B and IEC 61508 certified up to SIL 2 by TÜV SÜD. It includes hardware safety features such as memory POST, ERAD, BGCRC, and reciprocal ADC comparison - enabling systematic integration into functional safety architectures without requiring lockstep CPU redundancy.
F28P650SH7ZEJR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 256-LFBGA
- Series:
- C2000™ C28x Piccolo™, Functional Safety (FuSa)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- C28x
- Core Size:
- 32-Bit
- Speed:
- 200MHz
- Connectivity:
- CANbus, I2C, SCI, SPI, UART/USART, USB
- Peripherals:
- AES, Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 163
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 244K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.8V ~ 3.63V
- Data Converters:
- A/D 40x12/16b SAR; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
F28P650SH7ZEJR FAQ
1.How can I place an order for F28P650SH7ZEJR through Aetrix?
Please submit a Request for Quotation (RFQ) for F28P650SH7ZEJR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for F28P650SH7ZEJR reliable?
The price and inventory of F28P650SH7ZEJR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for F28P650SH7ZEJR is usually 5 days.
3.What payment methods are accepted for F28P650SH7ZEJR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for F28P650SH7ZEJR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for F28P650SH7ZEJR?
F28P650SH7ZEJR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your F28P650SH7ZEJR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for F28P650SH7ZEJR?
For technical support, including F28P650SH7ZEJR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your F28P650SH7ZEJR requirements.
6.How does Aetrix verify that F28P650SH7ZEJR is sourced from the original manufacturer or authorized distributors?
All F28P650SH7ZEJR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that F28P650SH7ZEJR meets industry standards.
7.What is the process for return or replacement of F28P650SH7ZEJR?
All F28P650SH7ZEJR units undergo pre-shipment inspection (PSI). If there is an issue with F28P650SH7ZEJR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The F28P650SH7ZEJR part is unused and in its original packaging.
Return procedure for F28P650SH7ZEJR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
F28P650SH7ZEJR Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

