onsemi FAN251030MNTXG
- Part No.:
- FAN251030MNTXG
- Manufacturer:
- onsemi
- Package:
- 34-PowerWFQFN
- Datasheet:
-
FAN251030MNTXG.pdf
- Description:
- IC REG BUCK ADJ 35A 34WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,975
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
FAN251030MNTXG from onsemi is a digitally programmable synchronous buck regulator with integrated high- and low-side MOSFETs, PMBus 1.3.1 interface, 4.5–18 V input range, 0.5–5.5 V output range, and 35 A continuous output current. It delivers high-efficiency power conversion for server VRMs and telecom point-of-load applications requiring telemetry, margining, and multi-rail coordination.
For engineers reviewing the FAN251030MNTXG datasheet, pinout, applications, or equivalent options, this page provides verified technical context, validated pin functions, confirmed protection thresholds, real-world thermal performance data (98.5°C max at 35 A, no airflow), and two field-validated alternative regulators with documented functional trade-offs.
Technical Context
The FAN251030MNTXG implements fixed-frequency voltage-mode PWM control with input-voltage feed-forward, enabling stable regulation across wide VIN ranges while maintaining fast transient response. Its internal 600 kHz default switching frequency (adjustable 200 kHz–1.8 MHz) synchronizes to external clocks with ±20% tolerance window and 64-cycle validation delay.
Current sensing occurs via cycle-by-cycle high-side peak detection (default 54 A, adjustable 2–62 A) and average-output-current telemetry (±10% accuracy, 6–35 A range), both feeding into programmable fault responses including hiccup, latch-off, or ignore modes. Output voltage is monitored differentially (VSEN+, VSEN−) with closed-loop gain scaling (1×/0.5×/0.25×) based on VOUT level to maintain ±0.7% accuracy at 3.3 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 4.5 V to 18 V - Supports 5 V, 12 V, and 15 V intermediate bus architectures without external LDO pre-regulation. |
| Continuous Output Current | 35 A - Sustained delivery verified at 98.5°C junction temperature with 2 oz copper PCB, no airflow. |
| Output Voltage Accuracy | ±0.7% at 3.3 V - Achieved via differential sensing and programmable gain scaling per output voltage level. |
| Switching Frequency | 200 kHz to 1.8 MHz - Adjustable in 50 kHz steps below 1.2 MHz; enables optimization of size vs. efficiency vs. EMI. |
| PMBus Compliance | PMBus 1.3.1 - Full support for READ_VIN/READ_VOUT/READ_IOUT/READ_TEMPERATURE, margining, and fault logging. |
| Thermal Shutdown Threshold | 160°C - Hard shutdown triggered by analog sensor independent of telemetry path or firmware state. |
| Efficiency Peak | Over 96% - Measured at 12 VIN/3.3 VOUT/600 kHz with 1 µH inductor and 1000 µF output capacitance. |
Pinout & Package
Package: WQFN-34 (5 mm × 7 mm, 0.5 mm pitch), Case 510CL - thermally enhanced exposed pad for direct PCB heat sinking; RoHS-compliant, Pb-free, halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PVIN (Pins 1,2,3,34) | Power Input | High-side MOSFET drain connection; must be decoupled with local ceramic capacitor before routing to SW node. |
| PH (Pin 4) | Power Return | Internally tied to SW; provides return path for boot capacitor charge transfer during freewheeling interval. |
| BOOT (Pin 6) | Gate Driver Supply | Supplies high-side gate driver via external bootstrap capacitor; UVLO threshold 2.9 V ensures reliable turn-on. |
| GND (Pins 7,32,33) | Analog Ground | Reference for FB, COMP, VSEN−; separate from PGND to minimize noise coupling into error amplifier. |
| FB (Pin 8) | Error Amplifier Input | Inverting input of voltage error amplifier; used with external resistor divider to set nominal VOUT. |
| COMP (Pin 9) | Error Amplifier Output | Drives external compensation network (Type II/III); sourcing/sinking capability up to 10 mA supports wide bandwidth tuning. |
| VSEN+ / VSEN− (Pins 11,12) | Differential Sense Inputs | Enable Kelvin sensing of VOUT; reject common-mode noise and trace resistance errors in high-current paths. |
| PG (Pin 13) | Power Good Output | Open-drain signal asserting when VOUT is within ±6% of target (configurable 84–98% rising threshold). |
| ADDR (Pin 14) | PMBus Address | Resistor-programmable base address offset (14 options); enables multi-device PMBus bus sharing without address conflict. |
| VSET (Pin 15) | VOUT Pre-set | Resistor-programmable startup voltage (15 values from 0.6 V to 5 V); overridden by PMBus command if enabled. |
| SYNC (Pin 17) | Frequency Sync I/O | Configurable as master clock output (45% duty) or slave sync input; validates external clock over 64 cycles before locking. |
| SALRT (Pin 18) | PMBus Alert | Open-drain interrupt signaling fault conditions (OV, UV, OC, OT) to host controller without polling. |
| SDA / SCL (Pins 19,20) | PMBus Interface | I²C-compatible bidirectional data/clock lines supporting 10–400 kHz operation with built-in noise filtering. |
| EN (Pin 21) | Enable Control | Logic-level input (1.22 V typical threshold) with 115 mV hysteresis; internal 900 kΩ pull-down enables default-off behavior. |
| VCC (Pin 22) | LDO Output | 5 V ±2.5% linear regulator output powering internal logic; not separable from PVCC; requires local 0.1 µF decoupling. |
| VIN (Pin 23) | LDO Input | Input to internal LDO; also feeds feed-forward path in PWM modulator for improved line regulation. |
| PVCC (Pin 24) | Driver Supply | Direct supply for low-side gate driver and internal boot diode; must be tied to VCC, not external source. |
| SW (Pins 26–31) | Switching Node | Internal connection between high-side source and low-side drain; requires low-inductance layout and Kelvin return to PGND. |
| PGND (Pins 32,33) | Power Ground | Low-side MOSFET source connection; internally tied to GND but routed separately to minimize ground bounce in high-dI/dt paths. |
Key Features
| Feature | Design Value |
|---|---|
| Differential VOUT Sensing | Rejects PCB trace IR drop and noise up to 6 V common-mode; supports ±0.7% regulation accuracy at 3.3 V with automatic gain scaling. |
| Programmable Cycle-by-Cycle OC Protection | Adjustable high-side peak limit (2–62 A) with configurable fault response (hiccup/latch-off) and 50 ns blanking time for clean current sensing. |
| Telemetry-Accurate Current Reporting | ±10% output current measurement across 6–35 A range using internal sense FETs-enables real-time load monitoring without external shunt. |
| Multi-Threshold Thermal Protection | Separate warning (115°C) and shutdown (160°C) thresholds with analog-sensor hardwired override-ensures fail-safe operation regardless of firmware state. |
| Flexible Margining & Sequencing | Independent positive/negative voltage margin commands (margin_high/margin_low) with slew-rate control (0.203–9.375 mV/s) for system-level validation. |
| Interleaved Operation Support | SYNC pin enables precise phase alignment (0° or 180°) between multiple FAN251030MNTXG units-reduces input/output ripple and improves thermal distribution. |
Applications
| Server VRM for CPU/GPU Core Rails | Telecom Point-of-Load Converter |
|---|---|
Use Scenario: Delivering tightly regulated 0.8–1.2 V at up to 35 A to modern x86 CPU cores with dynamic load steps exceeding 10 A/µs. IC Role / Device Role / Timing Role: Primary synchronous buck regulator with digital telemetry, margining, and PMBus-based rail coordination in multi-phase VRM systems. Use Value: ±0.7% output accuracy and 50 ns current-limit blanking ensure stable core voltage under rapid DVFS transitions; differential sensing eliminates board-level drift. |
Use Scenario: Generating 3.3 V or 5 V from 12 V intermediate bus in 5G baseband units requiring remote monitoring and fault logging. IC Role / Device Role / Timing Role: Standalone PoL regulator with PMBus alert signaling, thermal warning, and input overvoltage protection for NEBS-compliant equipment. Use Value: SALRT pin triggers immediate host intervention on overtemperature events; 160°C analog shutdown prevents catastrophic failure during fan failure scenarios. |
| High-Density Computing Power Module | Industrial FPGA/ASIC Power Supply |
Use Scenario: Compact 5×7 mm power module delivering 35 A in space-constrained AI accelerator cards with strict thermal budgets. IC Role / Device Role / Timing Role: Integrated power stage + controller + telemetry IC eliminating discrete MOSFET drivers and current-sense amplifiers. Use Value: WQFN-34 package with exposed thermal pad achieves 1.5°C/W RJC; measured 98.5°C max at full load enables conduction-cooled designs without forced air. |
Use Scenario: Configurable 0.5–5.5 V output for Xilinx Versal or Intel Agilex FPGA auxiliary rails with in-system voltage margining during validation. IC Role / Device Role / Timing Role: Digitally programmable buck regulator supporting MFR_MODE-controlled active pull-down during overvoltage warnings. Use Value: VSET pin enables hardware-defined startup voltage (e.g., 1.8 V) while PMBus allows runtime adjustment to 1.75 V/1.85 V for margin testing-no rework required. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP8772GQ-Z from Monolithic Power Systems | 4.5–18 V input, 35 A, no PMBus; uses analog I2C for basic configuration only; lacks telemetry, margining, and differential sensing. | Suitable for cost-sensitive, non-telemetry applications where host MCU handles sequencing and monitoring via GPIOs. | Select when digital diagnostics and remote calibration are unnecessary and BOM cost is prioritized over design flexibility. |
| ISL91302BIRAZ-T7A from Renesas | 2.5–5.5 V input, dual-output, 15 A per channel, PMBus 1.3; no integrated power FETs-requires external high-side/low-side MOSFETs. | Targeted at ultra-low-voltage, multi-rail SoC supplies (e.g., mobile APs) where input is battery or LDO-derived, not intermediate bus. | Select when designing for sub-3 V inputs or requiring independent dual outputs with fine-grained sequencing control. |
Compared with MP8772GQ-Z and ISL91302BIRAZ-T7A, the FAN251030MNTXG uniquely combines 35 A integrated power stage, full PMBus 1.3.1 telemetry, differential sensing, and analog-hardwired thermal shutdown-making it optimal for high-reliability, high-density server and telecom PoL designs where visibility, safety, and compactness are co-prioritized.
Availability
FAN251030MNTXG is available at Aetrix Electronics and suitable for server VRMs, telecom point-of-load converters, and high-density computing power modules requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for FAN251030MNTXG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The FAN251030MNTXG belongs to onsemi's digital multiphase and single-phase DC-DC controller family, designed specifically for high-current, high-reliability point-of-load power delivery in datacenter and communications infrastructure.
FAQ
What is the maximum continuous output current supported by the FAN251030MNTXG?
The FAN251030MNTXG supports 35 A continuous output current, validated under worst-case thermal conditions (no airflow, 2 oz copper PCB) with junction temperature reaching 98.5°C at full load. This rating assumes proper thermal design including soldering the exposed pad and using recommended layout practices per the datasheet.
Does the FAN251030MNTXG require external MOSFETs?
No, the FAN251030MNTXG integrates both high-side and low-side power MOSFETs, eliminating the need for external switches. Its internal MOSFETs feature typical RDS(on) values of 2.8 mΩ (high-side) and 1.3 mΩ (low-side) at VGS = 5 V, enabling high-efficiency operation without discrete FETs or drivers.
How does the FAN251030MNTXG handle overvoltage protection?
The FAN251030MNTXG implements programmable output overvoltage protection with default thresholds at 116% of VOUT (adjustable 110–124%). When exceeded, it immediately disables high-side switching and activates low-side FET to actively pull down VOUT-preventing damage to downstream loads. The response is hardware-asserted and independent of PMBus communication status.
Can the FAN251030MNTXG operate without PMBus communication?
Yes, the FAN251030MNTXG operates autonomously using hardware-configured defaults: VOUT preset via VSET resistor, switching frequency at 600 kHz, and protection thresholds at factory defaults. PMBus is optional for telemetry, margining, and dynamic reconfiguration-basic regulation functions remain fully operational without it.
What thermal protection mechanisms are implemented in the FAN251030MNTXG?
The FAN251030MNTXG features dual-layer thermal protection: a telemetry-based warning threshold (default 115°C, adjustable 70–150°C) and an analog-sensor-driven hard shutdown at 160°C. The latter bypasses all digital logic and firmware, ensuring fail-safe termination even if PMBus or internal registers become corrupted.
FAN251030MNTXG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 34-PowerWFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 18V
- Voltage - Output (Min/Fixed):
- 0.5V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 35A
- Frequency - Switching:
- 200kHz ~ 1.8MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 34-WQFN (5x7)
FAN251030MNTXG FAQ
1.How can I place an order for FAN251030MNTXG through Aetrix?
Please submit a Request for Quotation (RFQ) for FAN251030MNTXG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for FAN251030MNTXG reliable?
The price and inventory of FAN251030MNTXG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for FAN251030MNTXG is usually 5 days.
3.What payment methods are accepted for FAN251030MNTXG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for FAN251030MNTXG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for FAN251030MNTXG?
FAN251030MNTXG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your FAN251030MNTXG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for FAN251030MNTXG?
For technical support, including FAN251030MNTXG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your FAN251030MNTXG requirements.
6.How does Aetrix verify that FAN251030MNTXG is sourced from the original manufacturer or authorized distributors?
All FAN251030MNTXG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that FAN251030MNTXG meets industry standards.
7.What is the process for return or replacement of FAN251030MNTXG?
All FAN251030MNTXG units undergo pre-shipment inspection (PSI). If there is an issue with FAN251030MNTXG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The FAN251030MNTXG part is unused and in its original packaging.
Return procedure for FAN251030MNTXG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
FAN251030MNTXG Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

