onsemi FAN48630UC35X
- Part No.:
- FAN48630UC35X
- Manufacturer:
- onsemi
- Package:
- 16-UFBGA, WLCSP
- Datasheet:
-
FAN48630UC35X.pdf
- Description:
- IC REG BOOST PROG 1.5A 16WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:2,460
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
FAN48630UC35X from onsemi is a synchronous boost regulator with integrated power FETs, designed for single-cell Li-ion battery systems requiring 3.5 V fixed output at up to 1500 mA load current. It features true bypass mode, 2.5 MHz switching frequency, and low-quiescent-current forced bypass (4–10 µA) for extended battery life in portable electronics.
For engineers reviewing the FAN48630UC35X datasheet, pinout, applications, or equivalent options, key selection considerations include input voltage range (2.35–5.5 V), output accuracy (±4%), thermal shutdown thresholds (120 °C/100 °C hysteresis), soft-start timing (600 µs fast mode), and WLCSP-16 package compatibility with high-density PCB layouts.
Technical Context
The FAN48630UC35X operates in current-mode control with valley-current limiting and supports seamless transitions between continuous conduction mode (CCM) at 2.5 MHz and discontinuous conduction mode (DCM) at light loads. Its modulator logic manages four operating states: Linear Startup (LIN), Soft-Start (SS), Boost (BST), and Bypass (BPS), triggered by VIN relative to VOUT_TARGET and load conditions.
Bypass functionality is implemented via dual internal P-channel MOSFETs (Q1 and Q3), enabling sub-100 mΩ path resistance when VIN exceeds 3.5 V + 25 mV hysteresis. Forced Bypass Mode disables most bias circuitry except short-circuit protection (OCP On variant) or deactivates protections (Low IQ variant), depending on part suffix - FAN48630UC35X uses Low IQ configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 3.50 V / 3.70 V dual-setpoint; enables dynamic headroom optimization via VSEL pin during transients. |
| Max Load Current | 1500 mA at VIN = 2.6 V boosting to 3.5 V; validated under TJ < 120 °C for short-term operation. |
| Switching Frequency | 2.5 MHz typical; maintains CCM at moderate-to-heavy loads and reduces frequency in DCM for efficiency. |
| Quiescent Current | 4–10 µA in Forced Bypass Mode (Low IQ); extends battery runtime during system standby. |
| Input Voltage Range | 2.35 V to 5.5 V; supports full discharge curve of single-cell Li-ion (2.5–4.2 V) plus USB or adapter backup. |
| Efficiency | Up to 96% at 1000 mA, VIN = 3.6 V, VOUT = 3.5 V; optimized by synchronous rectification and low RDS(ON) switches. |
| Thermal Protection | 120 °C activation / 100 °C release (T120A/T120R); open-drain PG asserts LOW during overtemperature fault. |
Pinout & Package
Package: 16-bump Wafer-Level Chip-Scale Package (WLCSP), 1.78 × 1.78 × 0.586 mm, 0.4 mm pitch, case 567SY.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 (EN) | Enable control input | Logic-level enable (VIH ≥ 1.2 V, VIL ≤ 0.4 V); must be driven by 1.8 V logic - not connected directly to VIN. |
| A2 (PG) | Power Good indicator | Open-drain output pulled LOW during overload, thermal fault (>120 °C), or FAULT state; released HIGH after successful soft-start. |
| A3–A4 (VIN) | Main input supply | Connects to Li-ion battery anode; supports UVLO (2.35 V) and absolute max 6.5 V. |
| B1 (VSEL) | Output voltage select | Adjusts VOUT_TARGET upward in fixed steps to mitigate undershoot during load transients or line drops. |
| B2, C2, D1 (AGND) | Analog ground reference | Signal return for internal comparators and reference circuits; separate from PGND to minimize noise coupling. |
| B3–B4 (VOUT) | Regulated output | Delivers stable 3.5 V; requires COUT placed adjacent to PGND/VOUT pins per layout guidelines. |
| C1 (BYP) | Forced Bypass control | Pull LOW to activate Low IQ Forced Bypass Mode; device enters ultra-low-IQ state while maintaining VIN→VOUT conduction. |
| C3–C4 (SW) | Switching node | Connects to external 0.47 µH inductor; carries high di/dt; requires minimal trace length and tight loop area. |
| D2–D4 (PGND) | Power ground return | High-current return path for boost switch and sync rectifier; must connect COUT with shortest possible path. |
Key Features
| Feature | Design Value |
|---|---|
| True Bypass Operation | Enables direct VIN-to-VOUT conduction when VIN > 3.5 V + 25 mV hysteresis, reducing losses below 100 mΩ total path resistance. |
| Synchronous Rectification | Integrates low-RDS(ON) N-channel boost switch (85–120 mΩ) and P-channel sync rectifier (65–85 mΩ) to eliminate external Schottky loss. |
| Soft-Start with Load Disconnect | Prevents inrush current via controlled ramp-up; disconnects load during startup faults to avoid system brownout. |
| VSEL-Controlled Output Optimization | Allows real-time adjustment of VOUT_TARGET in 20 ms steps to balance transient response and quiescent power savings. |
| Short-Circuit Protection | Monitors VIN–VOUT drop across bypass FETs; asserts FAULT if >200 mV, preventing thermal runaway during output shorts. |
Applications
| USB OTG Power Supply | Smartphone Brownout Prevention |
|---|---|
Use Scenario: Portable device acts as USB host (e.g., camera, keyboard) drawing 500–1000 mA from single-cell Li-ion battery. IC Role / Device Role / Timing Role: Boost regulator providing stable 5 V (via VSEL-adjusted 3.5 V → LDO) while battery voltage drops below 3.3 V. Use Value: Eliminates need for external LDO or charge pump; maintains USB compliance during deep discharge without firmware intervention. |
Use Scenario: Mobile SoC experiences sudden CPU/GPU load surge causing instantaneous voltage sag on main rail. IC Role / Device Role / Timing Role: Fast-response boost stage holding system VDD above brownout threshold using VSEL-triggered VOUT step-up. Use Value: Prevents system reset or data corruption by delivering 1500 mA within 20 µs of VSEL assertion, leveraging pre-charged COUT. |
| Boosted Audio Amplifier Rail | LTE/3G RF Power Management |
Use Scenario: Class-D audio amplifier requires clean 3.5 V rail independent of battery voltage fluctuations during music playback. IC Role / Device Role / Timing Role: Low-noise, high-PSRR boost converter supplying dedicated analog rail with <50 mVpp ripple at 1 kHz. Use Value: Achieves >95 dB SNR by minimizing switching noise coupling via WLCSP layout and ceramic capacitor optimization. |
Use Scenario: Cellular modem transmits at peak power (e.g., LTE Cat.4 uplink), demanding transient current bursts up to 1.2 A. IC Role / Device Role / Timing Role: High-efficiency boost stage delivering regulated 3.5 V to PA bias rail with <±4% regulation during 500–1250 mA load steps. Use Value: Maintains RF output power stability and EVM performance across full battery range (2.5–4.2 V) without external compensation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar boost regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS61291DRVR | Fixed 3.5 V output, 1.2 MHz switching, 1200 mA max, 1.2 µA shutdown IQ; no forced bypass mode. | Lacks true bypass and VSEL control; suitable only where VIN never exceeds VOUT and ultra-low shutdown IQ is critical. | Choose TPS61291DRVR only if board space allows larger inductor and system does not require automatic or forced bypass transitions. |
| MAX17222ETA+T | 3.5 V output, 2.5 MHz, 1000 mA max, 2.5 µA shutdown IQ; includes bypass but no VSEL or PG pin. | Missing power-good signaling and VSEL-based transient headroom control; limited to simpler load profiles. | Select MAX17222ETA+T when PG monitoring and dynamic VOUT adjustment are unnecessary and 1000 mA load ceiling is acceptable. |
Compared with TPS61291DRVR and MAX17222ETA+T, the FAN48630UC35X uniquely combines 1500 mA capability, true bypass, VSEL-driven transient headroom control, and open-drain PG - making it optimal for battery-powered systems requiring robust brownout immunity and dynamic power management.
Availability
FAN48630UC35X is available at Aetrix Electronics and suitable for USB OTG power supplies, smartphone brownout prevention circuits, and boosted audio amplifier rails requiring stable component supply across production lifecycles.
Supply support for FAN48630UC35X includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensor, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The FAN48630UC35X belongs to the TINYBOOST® family of compact, high-frequency boost regulators engineered specifically for space-constrained portable electronics powered by advanced Li-ion batteries.
FAQ
What is the exact output voltage setting for FAN48630UC35X?
The FAN48630UC35X is factory-configured for dual-setpoint output: nominal 3.50 V with ±2% accuracy and a secondary target of 3.70 V. The VSEL pin allows dynamic selection between these points during operation to improve transient response without changing external components. This dual-voltage capability is confirmed in Table 1 of the official datasheet (FAN48630/D, Rev. 3, May 2024).
Does FAN48630UC35X support true bypass mode, and how is it activated?
Yes, the FAN48630UC35X supports true bypass mode both automatically and forcibly. Automatic bypass engages when VIN exceeds the target VOUT (3.5 V) plus 25 mV hysteresis and no switching has occurred for 5 seconds. Forced bypass is activated by pulling the BYP pin LOW, which places the device into ultra-low-IQ state (4–10 µA) while maintaining a low-resistance path from VIN to VOUT. Both modes are documented in the "Bypass Operation" section of the datasheet.
What package type and dimensions does FAN48630UC35X use?
The FAN48630UC35X uses a 16-bump Wafer-Level Chip-Scale Package (WLCSP) with 0.4 mm pitch, measuring 1.78 × 1.78 × 0.586 mm (case 567SY). Pin mapping follows a 4×4 bump array with specific assignments for EN, PG, VIN, VSEL, AGND, VOUT, BYP, SW, and PGND as shown in Figure 3 and Table 3 of the datasheet. This compact footprint supports high-density mobile PCB designs.
How does the soft-start behavior differ between FAN48630UC35X and slower variants like FAN48630UC45X?
The FAN48630UC35X uses the FAST soft-start option, achieving regulation in 600 µs with doubled LIN1/LIN2 phase currents versus SLOW variants. In contrast, FAN48630UC45X uses SLOW soft-start (1300 µs) to limit inrush current. This distinction is explicitly defined in Table 1's "Soft-Start" column and impacts system wake-up latency and input capacitor sizing requirements for the FAN48630UC35X.
What protection features are active in Forced Bypass Mode for FAN48630UC35X?
In Forced Bypass Mode, the FAN48630UC35X (Low IQ variant) disables short-circuit, UVLO, OVP, and overtemperature protections to minimize quiescent current. Only the basic conduction path remains active. This behavior is specified in the "Forced Bypass" subsection of the datasheet and differentiates it from OCP-On variants like FAN48630UC45X, where short-circuit protection remains enabled during bypass.
FAN48630UC35X Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- TinyBoost®
- Package/Case:
- 16-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Step-Up
- Output Configuration:
- Positive
- Topology:
- Boost
- Output Type:
- Programmable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.35V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 3.5V, 3.7V
- Voltage - Output (Max):
- -
- Current - Output:
- 1.5A (Switch)
- Frequency - Switching:
- 2.5MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WLCSP (1.78x1.78)
FAN48630UC35X FAQ
1.How can I place an order for FAN48630UC35X through Aetrix?
Please submit a Request for Quotation (RFQ) for FAN48630UC35X on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for FAN48630UC35X reliable?
The price and inventory of FAN48630UC35X are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for FAN48630UC35X is usually 5 days.
3.What payment methods are accepted for FAN48630UC35X?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for FAN48630UC35X transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for FAN48630UC35X?
FAN48630UC35X orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your FAN48630UC35X order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for FAN48630UC35X?
For technical support, including FAN48630UC35X datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your FAN48630UC35X requirements.
6.How does Aetrix verify that FAN48630UC35X is sourced from the original manufacturer or authorized distributors?
All FAN48630UC35X products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that FAN48630UC35X meets industry standards.
7.What is the process for return or replacement of FAN48630UC35X?
All FAN48630UC35X units undergo pre-shipment inspection (PSI). If there is an issue with FAN48630UC35X, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The FAN48630UC35X part is unused and in its original packaging.
Return procedure for FAN48630UC35X:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
FAN48630UC35X Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

