onsemi FAN53528EUC48X

Overview

FAN53528EUC48X from onsemi is a digitally programmable 3.0 A synchronous buck regulator with I²C interface, fixed 2.4 MHz switching frequency, and factory-default VOUT = 0.65 V. It operates from 2.5 V to 5.5 V input, delivers ±4% DC output accuracy across load and line, and supports PFM/PWM auto-mode transition for high efficiency down to 10 mA load - ideal for powering ARM and Tegra application processors.

For engineers reviewing the FAN53528EUC48X datasheet, pinout, applications, or equivalent options, key selection criteria include its 5 ms EN-to-VOUT startup delay, 6.25 mV programmable VOUT resolution (0.35–1.14375 V), 15-bump WLCSP package, and thermal shutdown at 150°C with 17°C hysteresis.

Technical Context

The FAN53528EUC48X uses a proprietary non-linear fixed-frequency PWM modulator with synchronous rectification, enabling stable 2.4 MHz operation independent of input voltage and load current. Its architecture supports seamless PFM-to-PWM mode transitions and eliminates ESR dependency for ceramic output capacitors.

It integrates hardware enable (EN pin with 250 kΩ internal pull-down), voltage-select logic (VSEL pin toggling between VSEL0/VSEL1 registers), and I²C slave address 0xA4. The device implements soft-start with 5 ms EN delay, programmable slew rate (0.5–64 mV/s), and output discharge control via OUTPUT_DISCHARGE bit.

Key Specifications

Pinout & Package

15-bump Wafer-Level Chip Scale Package (WLCSP), 1.310 mm × 2.015 mm, 0.4 mm ball pitch, Case 567QS.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar digitally programmable buck regulator applications.

Compared with TPS62864B0RQYR and RTQ2132BGQW, the FAN53528EUC48X uniquely combines factory-set 5 ms EN delay, ultra-low 50 µA PFM quiescent current, and seamless auto-mode transition - making it optimal for mobile SoC core rails requiring both sequencing control and battery longevity.

Availability

FAN53528EUC48X is available at Aetrix Electronics and suitable for mobile processor core rails, LPDDR memory supplies, and ultra-mobile PC platforms requiring stable component supply, long-term lifecycle support, and guaranteed WLCSP packaging consistency.

Supply support for FAN53528EUC48X includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.

The FAN53528 belongs to onsemi's high-efficiency, digitally programmable DC-DC converter product line, designed specifically for dynamic voltage scaling in mobile and embedded SoCs where precision, compactness, and low-light-load power consumption are critical.

FAQ

What is the default output voltage of the FAN53528EUC48X at power-up?

The FAN53528EUC48X powers up with VOUT = 0.65 V by default, as configured by the VSEL0 register. This value is selected because the VSEL pin is internally pulled down (250 kΩ), causing the device to read VSEL0 instead of VSEL1. The 0.65 V setting aligns with common ARM core rail requirements and is confirmed in the Ordering Information table on page 2 of the datasheet. FAN53528EUC48X maintains this default until reprogrammed via I²C.

Does the FAN53528EUC48X support true PFM mode, and how does it affect efficiency?

Yes, the FAN53528EUC48X supports true single-pulse PFM mode at light loads (<100 mA), achieving 50 µA typical quiescent current and maintaining >80% efficiency down to 10 mA. In PFM, the regulator delivers energy in discrete pulses rather than continuous switching, reducing switching losses. This behavior is verified in Figure 5 (Efficiency vs. Load Current) and Table 7 (IQ = 50 µA). FAN53528EUC48X automatically transitions to fixed-frequency PWM above ~100 mA, ensuring consistent EMI profile at higher loads.

What is the significance of the "5 ms EN delay" specified for the FAN53528EUC48X?

The 5 ms EN delay is a factory-programmed timing parameter unique to the FAN53528EUC48X variant. It defines the interval between the EN pin rising to logic high and the start of VOUT soft-start ramp-up. This delay enables deterministic power sequencing in multi-regulator systems - for example, allowing an always-on LDO to stabilize before the FAN53528EUC48X begins its 0.65 V ramp. The delay is documented in Table 6 and Figure 17 (Startup waveform), and is not present in other variants like FAN53528BUC08X or FAN53528GUC48X.

Can the FAN53528EUC48X be used with ceramic output capacitors, and why?

Yes, the FAN53528EUC48X is explicitly designed for ceramic output capacitors, as stated in the Operating Description: "The regulator performance is independent of the output capacitor ESR." This is achieved through its proprietary non-linear PWM modulator, which eliminates ESR-based compensation requirements. Recommended designs use two 22 µF X5R 0603 ceramics plus four 100 µF 0201 ceramics (Table 1), confirming full compatibility. Using ceramic capacitors reduces board area, improves transient response, and avoids electrolytic aging issues - all validated in Figure 14 (Load Transient) and Table 8 (VOUT_LOAD = ±20 mV).

What I²C slave address does the FAN53528EUC48X use, and how is it determined?

The FAN53528EUC48X uses I²C slave address 0xA4 (7-bit address 0x52, R/W bit appended), as specified in Table 12 of the datasheet. This address applies to all DUCxx, EUCxx, and GUCxx variants, distinguishing them from BUCxx parts (0xA0). The address is hardwired and cannot be changed via pins or registers. Communication is verified using standard I²C protocols up to 3.4 Mbps (High-Speed Mode), with timing parameters fully defined in Table 9. FAN53528EUC48X supports START, REPEATED START, ACK/NACK, and STOP conditions per Figures 20–22.