onsemi FAN53730UCX

Overview

FAN53730UCX from onsemi is an I²C-controlled 3 A synchronous buck regulator with constant-on-time (COT) topology, supporting 2.3 V–5.5 V input and programmable 0.3 V–2.0 V output. It delivers fast transient response, 2.5 MHz switching in FCCM, and integrated fault protection for LPDDR memory power rails in mobile SoC designs.

For engineers reviewing the FAN53730UCX datasheet, pinout, applications, or equivalent options, key selection considerations include I²C programmability of VSET1/VSET2 (1.00 V / 1.05 V), audio reduction mode (ARM), dynamic voltage scaling (DVS) with 8 slew rates, forced CCM control via register or SDA/FCCM pin, and WLCSP12 package thermal performance (θ_JA = 130°C/W).

Technical Context

The FAN53730UCX implements a variable-frequency COT control architecture that adjusts high-side on-time (t_ON = 70–202 ns) based on VIN and VOUT to maintain ~2.5 MHz operation near nominal conditions. Its valley-current-limited power stage supports dual current thresholds (4.6 A / 2.3 A) selectable via I²C register VAL_ILIM.

Integrated features include programmable Power Good polarity (PG_POL), 12.8 µA active quiescent current in DCM, soft-start ramp (~800 µs to 95% VOUT), and fault management with 40 µs timeout for short-circuit, overcurrent, UVLO, and thermal events (T_SD = 150°C, hysteresis = 30°C).

Key Specifications

Pinout & Package

Package: 12-bump WLCSP (1.07 mm × 1.36 mm, 0.35 mm pitch, Case 567GK), bottom-side solder bumps, Pb-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar buck regulator applications.

Compared with TPS6286418RTER and RTQ2132BWGE, the FAN53730UCX uniquely combines WLCSP12 size, I²C-based DVS/ARM/FCCM control, and dual-VSET defaults - making it optimal for space-constrained mobile memory power where dynamic rail tuning and acoustic noise elimination are mandatory.

Availability

FAN53730UCX is available at Aetrix Electronics and suitable for LPDDR memory power, mobile application processor core supplies, and RF module bias applications requiring stable component supply across high-volume consumer electronics production cycles.

Supply support for FAN53730UCX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi is a global semiconductor leader focused on energy-efficient innovation for automotive, industrial, cloud, and mobile end markets, with deep expertise in power management and analog solutions.

The FAN53730UCX belongs to onsemi's high-density mobile power management portfolio, engineered specifically for advanced LPDDR memory subsystems in next-generation smartphones and ultra-thin computing platforms.

FAQ

What is the default I²C address for the FAN53730UCX?

The FAN53730UCX has a fixed I²C slave address of 7'h20 (0x40). This address is factory-programmed and not user-modifiable. All register reads and writes to the FAN53730UCX must use this address on the I²C bus. The device supports Fast Mode Plus timing (up to 1 MHz), enabling rapid configuration of DVS, ARM, and FCCM settings during system boot.

Does the FAN53730UCX support dynamic voltage scaling (DVS) for both increasing and decreasing output voltage?

Yes, the FAN53730UCX supports bidirectional DVS: it can ramp VOUT up or down in 10 mV steps with programmable dwell time per step (2–16 s). When transitioning from 0.5 V to 1.0 V, the FAN53730UCX increments through each intermediate 10 mV setpoint; the same mechanism applies for downward transitions, ensuring monotonic, glitch-free rail changes required by LPDDR specifications.

How does the Audio Reduction Mode (ARM) function in the FAN53730UCX?

The FAN53730UCX implements ARM by monitoring idle time between switching cycles. If the dead time exceeds a programmable threshold (25 µs or 40 µs), the low-side FET is forced on to discharge VOUT slightly, triggering a new switching event. This enforces a minimum effective frequency of 25 kHz or 40 kHz - eliminating audible piezoelectric noise from ceramic capacitors without compromising regulation accuracy.

What is the maximum junction temperature and thermal shutdown behavior of the FAN53730UCX?

Thermal shutdown activates at TJ = 150°C with 30°C hysteresis, meaning the FAN53730UCX resumes operation only after die temperature falls to 120°C. This behavior is hardware-enforced and independent of I²C control. The WLCSP12 package achieves θ_JA = 130°C/W on standard 2s2p PCBs, requiring careful copper pour and thermal vias under the die for sustained 3 A operation at +85°C ambient.

Can the FAN53730UCX operate with input voltage below 2.3 V?

No - the FAN53730UCX incorporates an under-voltage lockout (UVLO) with a rising threshold of 2.3 V and hysteresis of 100 mV. If VIN drops below 2.1 V, the device shuts down and disables switching. Operation below 2.3 V is not characterized or guaranteed; attempting to bias the FAN53730UCX below this threshold may result in unregulated output, increased quiescent current, or latch-up.