onsemi FAN65005A
- Part No.:
- FAN65005A
- Manufacturer:
- onsemi
- Package:
- 35-PowerWFQFN
- Datasheet:
-
FAN65005A.pdf
- Description:
- IC REG BUCK ADJ 8A 35PQFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,517
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Product details
Overview
FAN65005A from onsemi is a synchronous PWM buck regulator IC integrating controller, high-side and low-side PowerTrench® MOSFETs, dual LDOs, and current-sense circuitry. It operates from 4.5 V to 65 V input, delivers up to 8 A continuous output current, features 0.6 V ±0.67% reference accuracy, adjustable 100 kHz–1 MHz switching frequency, and supports pre-bias startup - used in high-voltage POL modules for telecom base stations.
For engineers reviewing the FAN65005A datasheet, pinout, applications, or equivalent options, key selection considerations include its voltage-mode PWM control with VIN feed-forward, cycle-by-cycle overcurrent protection, thermal shutdown, and dual-LDO power management enabling single-supply operation across wide input ranges.
Technical Context
The FAN65005A implements fixed-frequency voltage-mode PWM control with input voltage feed-forward compensation, enabling stable regulation across its 4.5 V–65 V input range. Its error amplifier (GBW = 10 MHz, DC gain = 80 dB) drives an external compensation network at the COMP pin for loop tuning.
It integrates two LDOs: LDO1 (HVBIAS input, 5.0 V ±2.5%, dropout ≤2.0 V at 150 mA) and LDO2 (EXTBIAS input, switchover at 4.7 V), with automatic selection logic based on input voltages. Protection includes hiccup-mode OCP (1024-cycle delay before latch), thermal shutdown at 150°C, and dual-level OVP (115% and 130% VREF).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 65 V - supports wide-range industrial and telecom inputs without external pre-regulation |
| Output Current | 8 A continuous - enables compact high-power-density point-of-load conversion |
| Reference Voltage | 0.6 V ±0.67% - ensures tight output regulation (±3.6 mV) over −40°C to +125°C |
| Switching Frequency | 100 kHz to 1 MHz - adjustable via RT resistor; allows optimization of size vs. efficiency trade-offs |
| Protection Features | OCP (cycle-by-cycle + hiccup), OTP (150°C), UVLO (HVBIAS: 3.92 V), OVP (115%/130% VREF), UVP (35% VREF) |
| Package | 6 mm × 6 mm PQFN-35 - thermally enhanced for high-power dissipation in space-constrained designs |
| Control Scheme | Voltage-mode PWM with VIN feed-forward - improves line transient response across full input range |
Pinout & Package
Package: 6 mm × 6 mm PQFN-35 (Case 483BE), thermally enhanced with exposed PGND pad for efficient heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pads 1–3, 31–35) | Main power input | Connects directly to 4.5–65 V system rail; multiple pads reduce IR drop and improve current handling |
| PGND (Pads 4–6) | Power ground return | Low-inductance path for high-side/low-side MOSFETs and PVCC; critical for EMI and thermal performance |
| SW (Pins 7–10) | Switching node | Junction of integrated high-side and low-side MOSFETs; connects to inductor and output filter |
| PH (Pin 30) | High-side source | Provides bootstrap capacitor return path; must be tied directly to SW for proper high-side gate drive |
| BOOT (Pin 29) | Bootstrap supply | Drives high-side gate via external capacitor to PH; UVLO threshold 3.2 V (w.r.t. PH) |
| ILIM (Pin 14) | Peak current limit set | Resistor-to-GND sets high-side MOSFET current limit (kILIM_HS = 59.5 A/Ω) |
| FB (Pin 15) | Feedback input | Monitors output voltage; internal 0.6 V reference enables precise regulation via resistive divider |
| COMP (Pin 16) | Error amplifier output | External compensation node - connects RC network to tune loop stability and transient response |
| EN/UVLO (Pin 22) | Enable / input UVLO | 1.22 V threshold enables device or sets system input turn-on voltage (e.g., 35 V via resistor divider) |
| PGOOD (Pin 20) | Power-good indicator | Open-drain output asserts HIGH when FB is within 94–115% VREF; 500 µs delay and 5 µs deglitch |
Key Features
| Feature | Design Value |
|---|---|
| Voltage-mode PWM with VIN feed-forward | Improves line regulation and transient response across 4.5–65 V input without requiring complex loop redesign |
| Dual LDO architecture (HVBIAS + EXTBIAS) | Enables flexible biasing: LDO1 powers gate driver (PVCC); LDO2 reduces loss when VO ≥ 5 V, selectable automatically |
| Pre-bias startup capability | Supports hot-swap and battery-backed systems by forcing both MOSFETs OFF until SS voltage reaches pre-biased FB level |
| Adjustable soft-start (SS pin) | 5 µA constant-current ramp enables programmable startup time and prevents inrush current into pre-charged outputs |
| Programmable frequency synchronization | MODE pin selects master/non-master sync mode; SYNC pin accepts 70–130% of RT-set frequency for multi-phase coordination |
Applications
| Telecom Base Station Power | Industrial Automation PSU |
|---|---|
|
Use Scenario: Primary 48 V-to-12 V/5 V conversion in distributed power architecture of macrocell base stations. IC Role / Device Role / Timing Role: Synchronous buck regulator delivering 8 A at 5 V with <1% load/line regulation under RF burst loading. Use Value: Integrated MOSFETs and dual LDOs eliminate 6+ external components; 6×6 mm PQFN enables dense board layout in constrained RF chassis. |
Use Scenario: Field-programmable gate array (FPGA) core voltage supply in PLC backplanes operating from 24–60 V industrial rails. IC Role / Device Role / Timing Role: High-efficiency POL converter with pre-bias startup supporting hot-plug I/O modules and brownout recovery. Use Value: 0.67% reference accuracy and 100 kHz–1 MHz frequency adjustability ensure stable 1.0 V ±30 mV FPGA core rail across temperature and input variation. |
| USB-PD Programmable Power Supply | High-Voltage Battery Management System |
|
Use Scenario: Secondary-side 20 V-to-5 V/9 V/15 V conversion in USB-PD sink adapters supporting variable output protocols. IC Role / Device Role / Timing Role: Adjustable-frequency buck regulator synchronized to system clock for EMI reduction during dynamic voltage transitions. Use Value: SYNC pin enables deterministic frequency alignment with USB-PD controller; PGOOD output signals valid output to protocol IC. |
Use Scenario: Auxiliary 48 V-to-3.3 V/5 V supply for microcontroller, CAN transceiver, and cell monitoring ICs in 48 V Li-ion battery packs. IC Role / Device Role / Timing Role: Robust buck regulator with 150°C thermal shutdown and hiccup-mode OCP protecting against shorted cell monitoring traces. Use Value: Dual LDOs allow direct connection to battery stack (HVBIAS) and regulated mid-rail (EXTBIAS), minimizing standby power loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPQ4316-AEC1 | Automotive-grade (AEC-Q100), 60 V max input, 6 A output, current-mode control, smaller 4×4 mm QFN | Lacks pre-bias startup, no dual-LDO architecture, lower current rating - suitable for automotive infotainment but not telecom POL | Choose MPQ4316-AEC1 only for AEC-Q100-compliant designs where 6 A suffices and VIN ≤ 60 V |
| LM5164QPWPRQ1 | 65 V input, 1 A output, external MOSFETs required, current-mode control, integrated FET driver only | Requires 4+ external power components; lacks integrated MOSFETs, current sense, and dual LDOs - higher BOM cost and layout complexity | Choose LM5164QPWPRQ1 only when >8 A output or custom MOSFET selection is mandatory |
Compared with MPQ4316-AEC1 and LM5164QPWPRQ1, the FAN65005A delivers higher output current (8 A vs. 6 A/1 A), eliminates external power MOSFETs and sense resistors, and provides dual-LDO flexibility - making it optimal for space- and component-count-constrained high-voltage POL applications.
Availability
FAN65005A is available at Aetrix Electronics and suitable for telecom base station power supplies, industrial automation PSUs, and USB-PD programmable power supplies requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for FAN65005A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi is a global semiconductor supplier focused on energy-efficient innovation, delivering silicon solutions for automotive, industrial, cloud, and IoT applications.
The FAN65005A belongs to onsemi's high-voltage synchronous buck regulator product line, designed specifically for compact, high-efficiency point-of-load conversion in telecom infrastructure, industrial equipment, and battery-powered systems operating up to 65 V.
FAQ
What is the maximum input voltage rating for the FAN65005A?
The FAN65005A has an absolute maximum VIN rating of 70 V, but its recommended operating input voltage range is 4.5 V to 65 V. Operation above 65 V may compromise reliability and is not guaranteed per datasheet specifications. The HVBIAS pin shares this 65 V max operating limit and must be connected to VIN through an RC filter for feed-forward stability.
Does the FAN65005A support pre-bias startup, and how does it behave?
Yes, the FAN65005A supports pre-bias startup. When enabled, it forces both high-side and low-side MOSFETs OFF until the SS pin voltage ramps up to match the pre-existing FB voltage. Only then does normal soft-start commence. This prevents reverse current flow and ensures controlled ramp-up in hot-swap or battery-backed systems where the output rail is already energized before FAN65005A enable.
How is the switching frequency set and synchronized on the FAN65005A?
The FAN65005A switching frequency is set by an external resistor (RT) from pin 19 to AGND, enabling 100 kHz–1 MHz adjustment. For synchronization, the MODE pin configures master/non-master mode (70–130 kΩ), and the SYNC pin accepts or outputs a clock signal aligned to 70–130% of the RT-set frequency - allowing deterministic multi-phase coordination without external timing ICs.
What protection features are integrated into the FAN65005A?
The FAN65005A integrates overcurrent protection (cycle-by-cycle + hiccup mode after 1024 cycles), thermal shutdown (150°C with 20°C hysteresis), input UVLO (HVBIAS: 3.92 V), output overvoltage protection (OVP1 at 115% VREF, OVP2 at 130% VREF), undervoltage protection (UVP at 35% VREF), and short-circuit protection. All protections are internally implemented with no external components required.
Can the FAN65005A operate with only one LDO enabled, and how is LDO selection determined?
Yes, the FAN65005A can operate with only LDO1 enabled by leaving EXTBIAS open. LDO selection is automatic: LDO1 is active when EXTBIAS < 4.7 V or open; LDO2 activates when EXTBIAS ≥ 4.7 V and > HVBIAS. Both LDOs operate in switch mode below 5.4 V input to minimize dropout. The device delivers up to 150 mA from either LDO, with PVCC supplying the gate driver and VCC powering analog circuits.
FAN65005A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 35-PowerWFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 65V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 32.5V
- Current - Output:
- 8A
- Frequency - Switching:
- 100kHz ~ 1MHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 35-PQFN (6x6)
FAN65005A FAQ
1.How can I place an order for FAN65005A through Aetrix?
Please submit a Request for Quotation (RFQ) for FAN65005A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for FAN65005A reliable?
The price and inventory of FAN65005A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for FAN65005A is usually 5 days.
3.What payment methods are accepted for FAN65005A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for FAN65005A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for FAN65005A?
FAN65005A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your FAN65005A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for FAN65005A?
For technical support, including FAN65005A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your FAN65005A requirements.
6.How does Aetrix verify that FAN65005A is sourced from the original manufacturer or authorized distributors?
All FAN65005A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that FAN65005A meets industry standards.
7.What is the process for return or replacement of FAN65005A?
All FAN65005A units undergo pre-shipment inspection (PSI). If there is an issue with FAN65005A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The FAN65005A part is unused and in its original packaging.
Return procedure for FAN65005A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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