NXP Semiconductors FS32K146HRT0MLHT

Overview

FS32K146HRT0MLHT from NXP Semiconductors is an automotive-grade 32-bit Arm® Cortex-M4F microcontroller with 2 MB flash, 256 KB SRAM (both with ECC), 112 MHz HSRUN/80 MHz RUN operation, and integrated CSEc security engine. It supports CAN-FD, FlexCAN, LPUART/LIN, LPSPI, LPI2C, FlexIO, and 12-bit ADCs - deployed in vehicle body control modules requiring ASIL-B functional safety compliance.

For engineers reviewing the FS32K146HRT0MLHT datasheet, FS32K146HRT0MLHT pinout, FS32K146HRT0MLHT application, or FS32K146HRT0MLHT equivalent, key selection criteria include its -40 °C to +125 °C ambient rating (M-grade), 100-pin LQFP package, dual-core debug support (SWD/JTAG), and mandatory mode-switching (RUN at 80 MHz) for CSEc security operations and EEPROM emulation.

Technical Context

The FS32K146HRT0MLHT implements a dual-voltage domain architecture with separate VDD/VDDA supplies (2.7–5.5 V), enabling robust analog performance alongside high-speed digital execution. Its clock system integrates FIRC (48 MHz), SIRC (8 MHz), LPO (128 kHz), SOSC (4–40 MHz), and SPLL (up to 112 MHz), with configurable gating per peripheral.

Power management includes five operational modes (HSRUN, RUN, STOP, VLPR, VLPS), where HSRUN enables peak 112 MHz CPU performance but disables CSEc and EEPROM writes - requiring explicit transition to RUN mode (80 MHz) for secure boot or data flash updates. The System MPU enforces memory protection at the crossbar switch level across all masters (CPU, DMA, Ethernet).

Key Specifications

Pinout & Package

FS32K146HRT0MLHT is housed in a 100-pin LQFP package (14 × 14 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow the S32K14x family standard layout, supporting full GPIO remapping via I/O signal multiplexing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar automotive microcontroller applications.

Compared with FS32K146HRT0MLHT, the S32K144HRT0MLHT offers reduced memory and peripheral count at lower cost for simpler nodes, while the S32K148HRT0MLHT extends functionality with Ethernet and audio - all share identical M-grade thermal rating, CSEc security, and 100-pin LQFP mechanical compatibility.

Availability

FS32K146HRT0MLHT is available at Aetrix Electronics and suitable for automotive body control, electric power steering, ADAS sensor hubs, and vehicle gateway applications requiring stable component supply across extended product lifecycles.

Supply support for FS32K146HRT0MLHT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure, reliable, and energy-efficient processing solutions for automotive, industrial, and IoT markets.

The S32K1xx family is designed specifically for automotive electronic control units requiring functional safety (ASIL-B), security (SHE-compliant CSEc), and real-time performance - targeting body, chassis, and ADAS domains with scalable memory and peripheral options.

FAQ

What is the maximum operating frequency of the FS32K146HRT0MLHT and under what conditions?

The FS32K146HRT0MLHT operates at up to 112 MHz in HSRUN mode and 80 MHz in RUN mode. HSRUN mode is restricted: CSEc security operations and EEPROM emulation require switching to RUN mode (80 MHz) to avoid error flag generation. This behavior is documented in the S32K1xx Data Sheet Rev. 15 and applies specifically to FS32K146HRT0MLHT due to its M-grade thermal specification and integrated CSEc engine.

Does the FS32K146HRT0MLHT support CAN-FD, and how many CAN interfaces does it include?

Yes, the FS32K146HRT0MLHT includes three FlexCAN modules, each supporting CAN-FD (ISO 11898-1) up to 5 Mbps. All three are fully functional in the 100-pin LQFP package, with dedicated TX/RX pins mapped to physical pins per the S32K14x IO Signal Description document. This enables multi-bus domain separation - for example, one for powertrain, one for chassis, and one for body networks - within a single FS32K146HRT0MLHT device.

What is the ambient temperature range and qualification grade for the FS32K146HRT0MLHT?

The FS32K146HRT0MLHT is rated for -40 °C to +125 °C ambient temperature (M-grade), with a maximum junction temperature of 135 °C in RUN mode. This qualification aligns with AEC-Q100 Grade 1 requirements and is validated for under-hood automotive applications. The device's thermal characteristics are specified in Table 5 of the S32K1xx Data Sheet Rev. 15, and the "M" in FS32K146HRT0MLHT explicitly denotes this extended temperature capability.

How does the CSEc (Cryptographic Services Engine) function on the FS32K146HRT0MLHT, and what are its limitations?

The CSEc on FS32K146HRT0MLHT implements SHE v3.1-compliant cryptographic functions including AES-128/256, SHA-256, ECDSA, and TRNG. It requires operation in RUN mode (80 MHz); attempting CSEc execution in HSRUN mode (112 MHz) triggers error flags and halts secure operations. This limitation is inherent to the FS32K146HRT0MLHT silicon design and is documented in multiple sections of the S32K1xx Data Sheet Rev. 15, including Features, Block Diagram notes, and Ordering Information.

What package type and pin count does the FS32K146HRT0MLHT use, and is it pin-compatible with other S32K14x devices?

The FS32K146HRT0MLHT uses a 100-pin LQFP package (14 × 14 mm, 0.5 mm pitch) with exposed thermal pad. It is pin-to-pin compatible with all other S32K14x devices offered in the same 100-pin LQFP variant - including S32K142HRT0MLHT, S32K144HRT0MLHT, and S32K148HRT0MLHT - enabling hardware reuse across memory/peripheral variants without PCB redesign. This compatibility is confirmed in Figure 3 of the S32K1xx Data Sheet Rev. 15.