My Inquiry
My Account
NXP Semiconductors FS32K146HRT0MLQR
- Part No.:
- FS32K146HRT0MLQR
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
FS32K146HRT0MLQR.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 144LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,480
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
FS32K146HRT0MLQR from NXP Semiconductors is an automotive-grade 32-bit Arm Cortex-M4F microcontroller with 2 MB flash, 256 KB SRAM (both with ECC), and dual 12-bit ADCs supporting up to 32 channels each. It operates at up to 112 MHz in HSRUN mode and supports CAN-FD, FlexCAN, LPUART/LIN, LPSPI, LPI2C, FlexIO, and cryptographic services via CSEc - deployed in engine control units, battery management systems, and vehicle body controllers.
For engineers reviewing the FS32K146HRT0MLQR datasheet, FS32K146HRT0MLQR pinout, FS32K146HRT0MLQR application, or FS32K146HRT0MLQR equivalent, key selection considerations include its -40 °C to +125 °C extended temperature rating (M-grade), 100-pin LQFP package, ASIL-B capable safety architecture, and mandatory RUN-mode (80 MHz) execution for CSEc security operations or EEPROM emulation.
Technical Context
The FS32K146HRT0MLQR implements a dual-core Arm Cortex-M4F/M0+ architecture with integrated FPU, DSP extensions, and configurable NVIC. Its clock system includes SOSC (4–40 MHz), FIRC (48 MHz), SIRC (8 MHz), LPO (128 kHz), and SPLL enabling up to 112 MHz system frequency in HSRUN mode.
Power management uses PMC with five modes (HSRUN, RUN, STOP, VLPR, VLPS); memory protection relies on NXP's system MPU at the crossbar switch level-not Arm Core MPU-enforcing access rights per master (Core, DMA, Ethernet). CSEc security and EEPROM writes require explicit transition from HSRUN to RUN mode (80 MHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M4F with single-precision FPU and DSP extensions; enables real-time motor control and sensor fusion algorithms. |
| Max Clock Frequency | 112 MHz in HSRUN mode; requires voltage ≥2.7 V and ambient ≤125 °C - performance throttles to 80 MHz in RUN mode for security/EEPROM operations. |
| Flash Memory | 2 MB program flash with ECC; supports over-the-air (OTA) updates with error detection and correction for functional safety compliance. |
| SRAM & FlexRAM | 256 KB SRAM with ECC + 4 KB FlexRAM usable as SRAM or EEPROM emulation; critical for ASIL-B data integrity in automotive control loops. |
| Analog Peripherals | Two 12-bit SAR ADCs (1 Msps each, up to 32 inputs/module); one analog comparator with integrated 8-bit DAC for closed-loop voltage/current sensing. |
| Communication Interfaces | Three FlexCAN modules (CAN-FD capable), three LPUART/LIN, three LPSPI, two LPI2C, FlexIO, and optional 10/100 Mbps Ethernet with IEEE 1588 - suitable for domain controller interconnect. |
| Safety & Security | Cryptographic Services Engine (CSEc) compliant with SHE specification; System MPU, CRC module, WDOG, EWM, and ECC on flash/SRAM meet ISO 26262 ASIL-B requirements. |
Pinout & Package
FS32K146HRT0MLQR is housed in a 100-pin LQFP package (14 × 14 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are defined in the S32K1xx Reference Manual IO Signal Description sheets; all S32K14x devices sharing this package are pin-to-pin compatible.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VREFH | Power supply and analog reference | Must be shorted on PCB with decoupling; VDDA/VREFH ≤ VDD + 0.1 V ensures ADC accuracy across -40 °C to +125 °C. |
| RESET_B | Active-low reset input | Asynchronous reset signal; internal pull-up enables reliable power-on initialization without external circuitry. |
| SWD_CLK / SWD_DIO | Serial Wire Debug interface | Two-pin debug port supporting full JTAG/SWD functionality including trace (ITM, TPIU) and secure firmware updates. |
| CAN0_TX / CAN0_RX | FlexCAN channel 0 differential I/O | Direct connection to external CAN transceiver; supports ISO 11898-1 CAN-FD up to 5 Mbps with built-in loopback for self-test. |
| ADC0_SE0–ADC0_SE31 | Analog input channels (Bank 0) | 32 dedicated pins for high-resolution sensor acquisition; multiplexed with GPIO and other peripherals per configuration register. |
Key Features
| Feature | Design Value |
|---|---|
| ASIL-B Safety Architecture | System MPU enforces memory access rights per bus master (Core, DMA, Ethernet); CRC, ECC, WDOG, and EWM support fault detection and containment. |
| Flexible Power Modes | Five low-power states (HSRUN/RUN/STOP/VLPR/VLPS); dynamic clock gating and peripheral isolation reduce active current to <10 mA at 80 MHz. |
| Secure Boot & Cryptography | CSEc implements AES-128/256, SHA-256, RNG, and secure key storage; boot authentication prevents unauthorized firmware execution. |
| Robust Analog Subsystem | Dual 12-bit ADCs with hardware trigger synchronization, window compare, and calibration support - essential for precise battery cell monitoring and motor phase sensing. |
| Protocol Emulation | FlexIO module configures up to 8 pins as UART, SPI, I2C, I2S, LIN, or PWM; eliminates need for external protocol bridge ICs in cost-sensitive ECUs. |
Applications
| Engine Control Unit (ECU) | Electric Power Steering (EPS) |
|---|---|
Use Scenario: Real-time combustion timing, fuel injection pulse width, and knock detection using crank/cam position sensors and wideband O2 feedback. IC Role / Device Role / Timing Role: Primary control MCU executing deterministic PID loops at ≤100 µs intervals with synchronized ADC sampling and PWM output generation. Use Value: 112 MHz HSRUN mode delivers sufficient MIPS headroom for multi-sensor fusion while ECC-protected flash ensures OTA update reliability under harsh ECU thermal conditions. |
Use Scenario: Torque assist calculation, motor position tracking, and fault response within <5 ms latency during steering maneuvers. IC Role / Device Role / Timing Role: Safety-critical controller managing BLDC motor commutation, torque feedback, and CAN-FD communication with ADAS domain. Use Value: Dual ADC banks enable simultaneous sampling of motor phase currents and hall sensor signals; CSEc secures firmware against tampering in safety-critical drive-by-wire systems. |
| Battery Management System (BMS) | Vehicle Body Controller (VBC) |
Use Scenario: Cell voltage, temperature, and current monitoring across 12–96 series-connected Li-ion cells with balancing control. IC Role / Device Role / Timing Role: Central BMS MCU interfacing with analog front-end (AFE) via SPI, performing SOC/SOH estimation, and communicating via isolated CAN. Use Value: 256 KB ECC SRAM stores runtime state variables and calibration tables; FlexRAM emulates EEPROM for non-volatile fault logs without wear-out concerns. |
Use Scenario: Centralized control of lighting, door locks, HVAC, and window lift functions with LIN subnetwork coordination. IC Role / Device Role / Timing Role: High-pin-count general-purpose MCU managing >100 GPIOs, multiple LPUART/LIN buses, and PWM dimming outputs. Use Value: 156 GPIOs with interrupt capability and flexible pin muxing simplify wiring harness consolidation; LPI2C/LPSPI support low-power sensor polling during sleep states. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| FS32K148HRT0MLQR | 2 MB flash, 512 KB SRAM, 100-pin LQFP, adds 10/100 Mbps Ethernet MAC and dual SAI audio interfaces; same M-grade temp range and CSEc support. | Required for gateway or domain controller designs needing time-synchronized audio streaming or IEEE 1588-based network timing. | Select FS32K148HRT0MLQR only if Ethernet or SAI functionality is needed; otherwise FS32K146HRT0MLQR offers optimal cost/performance balance for standalone ECU/BMS roles. |
| FS32K144HRT0MLQR | 1 MB flash, 128 KB SRAM, 100-pin LQFP, retains dual ADCs, FlexCAN, CSEc, and ASIL-B safety features; no QuadSPI or HyperBus support. | Suitable for mid-tier ECUs where reduced memory footprint suffices and external high-speed memory expansion is unnecessary. | Choose FS32K144HRT0MLQR when application code size fits within 1 MB flash and system-level memory bandwidth demands are modest. |
Compared with FS32K148HRT0MLQR, FS32K146HRT0MLQR reduces SRAM by 256 KB and omits Ethernet/SAI but maintains identical safety architecture and CAN-FD capability; versus FS32K144HRT0MLQR, it doubles flash and SRAM while adding QuadSPI - making it ideal for complex OTA-updatable control software with large calibration tables.
Availability
FS32K146HRT0MLQR is available at Aetrix Electronics and suitable for engine control units, battery management systems, and electric power steering modules requiring stable component supply across automotive production lifecycles.
Supply support for FS32K146HRT0MLQR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in functional safety and automotive-grade reliability.
The S32K1xx family targets ASIL-B automotive control applications - designed from inception for engine management, chassis control, and electrification systems demanding robust real-time performance, security, and long-term supply stability.
FAQ
What is the maximum operating temperature for FS32K146HRT0MLQR?
The FS32K146HRT0MLQR is rated for ambient operation from -40 °C to +125 °C (M-grade). In HSRUN mode (112 MHz), junction temperature must not exceed 135 °C; in RUN mode (80 MHz), it supports up to 135 °C junction under the same ambient condition - verified per Table 5 of the S32K1xx Data Sheet Rev. 15.
Does FS32K146HRT0MLQR support CAN-FD?
Yes, FS32K146HRT0MLQR includes three FlexCAN modules that support CAN-FD per ISO 11898-1, enabling data rates up to 5 Mbps in FD mode. The 'F' in the ordering option Y-field confirms CAN-FD capability, and the device implements protocol arbitration, bit-rate switching, and flexible data-length fields as specified in the S32K1xx Reference Manual.
Can FS32K146HRT0MLQR execute CSEc security functions in HSRUN mode?
No. FS32K146HRT0MLQR triggers error flags if CSEc cryptographic operations or EEPROM writes/erase are attempted in HSRUN mode (112 MHz). The device must transition to RUN mode (80 MHz) before initiating these functions - a hardware-enforced restriction documented in Sections 1.1 and 3.1 of the S32K1xx Data Sheet.
What package type does FS32K146HRT0MLQR use?
FS32K146HRT0MLQR uses a 100-pin LQFP package (14 mm × 14 mm, 0.5 mm pitch) with exposed thermal pad. This package is shared across S32K14x devices and guarantees pin-to-pin compatibility with other members of the family, including FS32K144HRT0MLQR and FS32K148HRT0MLQR.
How much SRAM and flash memory does FS32K146HRT0MLQR provide?
FS32K146HRT0MLQR integrates 2 MB of program flash memory and 256 KB of SRAM - both protected by Error-Correcting Code (ECC). Additionally, it provides 4 KB of FlexRAM usable as SRAM or EEPROM emulation, and 64 KB of FlexNVM for data flash with ECC, as confirmed in Section 1.1 "Memory and memory interfaces" of the S32K1xx Data Sheet.
FS32K146HRT0MLQR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 144-LQFP
- Series:
- S32K
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4F
- Core Size:
- 32-Bit Single-Core
- Speed:
- 80MHz
- Connectivity:
- CANbus, FlexIO, I2C, LINbus, SPI, UART/USART
- Peripherals:
- POR, PWM, WDT
- Number of I/O:
- 128
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 24x12b SAR; D/A1x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
FS32K146HRT0MLQR FAQ
1.How can I place an order for FS32K146HRT0MLQR through Aetrix?
Please submit a Request for Quotation (RFQ) for FS32K146HRT0MLQR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for FS32K146HRT0MLQR reliable?
The price and inventory of FS32K146HRT0MLQR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for FS32K146HRT0MLQR is usually 5 days.
3.What payment methods are accepted for FS32K146HRT0MLQR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for FS32K146HRT0MLQR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for FS32K146HRT0MLQR?
FS32K146HRT0MLQR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your FS32K146HRT0MLQR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for FS32K146HRT0MLQR?
For technical support, including FS32K146HRT0MLQR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your FS32K146HRT0MLQR requirements.
6.How does Aetrix verify that FS32K146HRT0MLQR is sourced from the original manufacturer or authorized distributors?
All FS32K146HRT0MLQR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that FS32K146HRT0MLQR meets industry standards.
7.What is the process for return or replacement of FS32K146HRT0MLQR?
All FS32K146HRT0MLQR units undergo pre-shipment inspection (PSI). If there is an issue with FS32K146HRT0MLQR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The FS32K146HRT0MLQR part is unused and in its original packaging.
Return procedure for FS32K146HRT0MLQR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
FS32K146HRT0MLQR Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
