NXP Semiconductors FS32K146UAT0VLQR
- Part No.:
- FS32K146UAT0VLQR
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
FS32K146UAT0VLQR.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
FS32K146UAT0VLQR from NXP Semiconductors is an automotive-grade 32-bit Arm Cortex-M4F microcontroller with 2 MB flash, 256 KB SRAM (both with ECC), 112 MHz HSRUN operation, and integrated CSEc security engine. It features dual 12-bit ADCs (32-channel total), three FlexCAN modules (CAN-FD capable), and operates from -40 °C to 105 °C in LQFP-100 package - deployed in vehicle body control modules requiring functional safety up to ASIL-B.
For engineers reviewing the FS32K146UAT0VLQR datasheet, FS32K146UAT0VLQR pinout, FS32K146UAT0VLQR application, or FS32K146UAT0VLQR equivalent, key selection considerations include HSRUN/RUN mode switching constraints for CSEc/EEPROM operations, FlexCAN FD channel count per package, LQFP-100 I/O allocation (up to 81 GPIO), and voltage range compliance (2.7–5.5 V) under automotive transients.
Technical Context
The FS32K146UAT0VLQR implements a dual-core execution environment via Arm Cortex-M4F (primary) and M0+ (co-processor for low-power tasks), sharing AXBS-Lite crossbar and system MPU for memory protection across DMA, Ethernet, and core initiators. Its clock architecture integrates SPLL (up to 112 MHz), FIRC (48 MHz), SIRC (8 MHz), and LPO (128 kHz), with dynamic mode transitions between HSRUN, RUN, STOP, VLPR, and VLPS governed by PMC.
Peripherals are partitioned across power domains: FlexCAN, LPUART, LPSPI, and LPI2C retain functionality in low-power modes; QuadSPI with HyperBus™ supports external memory expansion; and safety mechanisms include ECC on flash/SRAM, CRC module, WDOG/EWM, and system MPU enforcing access rights per master-aligned with ISO 26262 ASIL-B requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | Arm Cortex-M4F with single-precision FPU and DSP extensions; delivers 1.25 DMIPS/MHz for real-time motor control loops. |
| Max Clock Speed | 112 MHz in HSRUN mode; requires downshift to 80 MHz RUN mode for CSEc cryptographic operations or EEPROM emulation writes. |
| Memory | 2 MB program flash with ECC; 64 KB FlexNVM with ECC and EEPROM emulation; 256 KB SRAM with ECC; 4 KB FlexRAM configurable as SRAM or EEPROM. |
| Analog Peripherals | Two 12-bit SAR ADCs (1 Msps each, up to 32 channels total); one analog comparator with integrated 8-bit DAC for sensor biasing. |
| Communication | Three FlexCAN modules (CAN-FD ISO 11898-1 compliant); three LPUART/LIN; three LPSPI; two LPI2C; QuadSPI with HyperBus™ interface. |
| Safety & Security | Cryptographic Services Engine (CSEc) supporting SHE-compliant AES/SHA/RSA; 128-bit unique ID; system MPU enforcing crossbar-level memory access control. |
| Package & Temp | 100-pin LQFP (14 × 14 mm, 0.5 mm pitch); industrial temperature grade (-40 °C to +105 °C ambient). |
Pinout & Package
FS32K146UAT0VLQR is housed in a 100-pin LQFP package (14 × 14 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per the S32K14x IO Signal Description multiplexing sheet; all pins support interrupt capability, and up to 81 are configurable as GPIO.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VREFH, VREFL | Power and reference supply inputs | Separate analog/digital rails required; VDD–VDDA differential must stay within ±0.1 V; VREFH ≤ VDDA + 0.1 V ensures ADC accuracy. |
| RESET_b, NMI_b | Asynchronous reset and non-maskable interrupt inputs | Low-active signals with internal pull-up; RESET_b assertion halts all clocks and resets core/peripherals; NMI_b triggers highest-priority exception. |
| SWD_CLK, SWD_IO | Serial Wire Debug interface | 2-pin debug port supporting JTAG/SWD protocols; enables full visibility into core state, memory, and peripheral registers during development and diagnostics. |
| CAN0_TX, CAN0_RX, CAN1_TX, CAN1_RX, CAN2_TX, CAN2_RX | FlexCAN transceiver signal pairs | Differential bus interfaces compliant with ISO 11898-1; support CAN-FD data rates up to 5 Mbps; require external termination and common-mode chokes. |
| ADC0_SE0–ADC0_SE31, ADC1_SE0–ADC1_SE31 | Analog input channels | Up to 32 single-ended inputs per ADC module; shared with GPIO; require proper PCB layout (guard ring, ground plane) for 12-bit linearity. |
Key Features
| Feature | Design Value |
|---|---|
| HSRUN/RUN Mode Switching | Enables 112 MHz real-time performance while mandating 80 MHz RUN mode for secure CSEc operations or FlexNVM writes-prevents simultaneous high-speed execution and flash programming conflicts. |
| System MPU Enforcement | NXP's crossbar-level MPU assigns distinct read/write/execute permissions per memory region for each master (core, DMA, Ethernet), satisfying ASIL-B memory isolation requirements without Arm Core MPU dependency. |
| FlexCAN FD Integration | Three independent FlexCAN modules support mixed classical CAN and CAN-FD frames on same bus; programmable bit timing allows backward compatibility and bandwidth scaling. |
| EEPROM Emulation | 64 KB FlexNVM + 4 KB FlexRAM provide wear-levelled, ECC-protected EEPROM replacement-eliminates external serial EEPROM in body control units. |
| Low-Power Timer Architecture | LPTMR, LPIT (4-channel), and RTC operate in VLPR/VLPS modes; PDB triggers ADC conversions or PWM updates without waking CPU-critical for battery-powered wake-on-event systems. |
Applications
| Body Control Module (BCM) | Electric Power Steering (EPS) |
|---|---|
|
Use Scenario: Centralized control of door locks, lighting, wipers, and HVAC actuators in 12 V automotive platforms. IC Role / Device Role / Timing Role: Main application MCU executing ASW-compliant firmware; manages LIN communication to slave nodes and monitors analog sensor inputs (potentiometers, thermistors). Use Value: 81 GPIO and three LPUART/LIN modules enable direct connection to 12+ LIN slaves; ECC memory ensures reliability over 15-year vehicle lifetime. |
Use Scenario: Real-time torque assist calculation and motor phase control in column-assist EPS systems. IC Role / Device Role / Timing Role: Safety-critical controller running ISO 26262 ASIL-B software; executes FOC algorithms at 10 kHz using FPU and FlexTimer PWM outputs. Use Value: 112 MHz HSRUN mode sustains deterministic loop timing; dual ADCs sample current/voltage simultaneously; CSEc secures firmware updates. |
| Advanced Driver Assistance Systems (ADAS) Sensor Hub | Vehicle Gateway Module |
|
Use Scenario: Aggregation and preprocessing of radar, camera, and ultrasonic sensor data before forwarding to domain controller. IC Role / Device Role / Timing Role: Peripheral co-processor offloading time-sensitive tasks (CAN message filtering, SPI sensor reads, timestamping) from main ADAS SoC. Use Value: FlexIO emulates custom sensor protocols; LPIT and PDB synchronize multi-sensor sampling; QuadSPI interfaces to local image buffer memory. |
Use Scenario: Protocol translation and firewall between high-speed Ethernet backbone and legacy CAN/LIN subnets in zonal architectures. IC Role / Device Role / Timing Role: Gateway MCU managing IEEE 1588 time synchronization, CAN-FD routing, and secure OTA update distribution. Use Value: Integrated 10/100 Mbps Ethernet MAC with hardware timestamping; three FlexCAN FD ports isolate domains; CSEc validates signed firmware images. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| FS32K148UAT0VLQR | 2 MB flash, 256 KB SRAM, 100-pin LQFP; adds 10/100 Mbps Ethernet MAC and two SAI audio interfaces not present in FS32K146UAT0VLQR. | Required where gateway functionality (IEEE 1588 sync, audio streaming) or higher I/O count (up to 156 GPIO) is needed beyond BCM/EPS scope. | Select FS32K148UAT0VLQR only if Ethernet or SAI peripherals are actively used; otherwise FS32K146UAT0VLQR reduces BOM cost and layout complexity. |
| FS32K144UAT0VLQR | 1 MB flash, 128 KB SRAM, 100-pin LQFP; retains identical peripheral set (three FlexCAN FD, dual ADC, CSEc) but halves memory resources. | Suitable for cost-optimized BCM variants with reduced feature sets (e.g., no EEPROM emulation, smaller firmware footprint). | Choose FS32K144UAT0VLQR when application firmware fits in 1 MB flash and 128 KB SRAM; verify FlexNVM usage does not exceed 32 KB D-flash allocation. |
Compared with FS32K146UAT0VLQR, FS32K148UAT0VLQR adds Ethernet/SAI at higher cost and power, while FS32K144UAT0VLQR reduces memory capacity without altering peripheral count-making FS32K146UAT0VLQR the balanced choice for mid-tier ASIL-B control applications requiring full feature headroom.
Availability
FS32K146UAT0VLQR is available at Aetrix Electronics and suitable for automotive body control, electric power steering, ADAS sensor hubs, and vehicle gateway modules requiring stable component supply across extended product lifecycles.
Supply support for FS32K146UAT0VLQR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and automotive-grade MCUs.
The S32K1xx family-including FS32K146UAT0VLQR-is designed specifically for automotive electronic control units requiring ASIL-B compliance, robust EMC performance, and long-term supply stability in harsh environments.
FAQ
What is the maximum operating frequency of the FS32K146UAT0VLQR, and under what conditions is it valid?
The FS32K146UAT0VLQR achieves 112 MHz in HSRUN mode, validated across -40 °C to +105 °C ambient and 2.7–5.5 V supply. However, this speed is incompatible with CSEc cryptographic operations or FlexNVM write/erase cycles; those functions require switching to 80 MHz RUN mode per NXP's specification. The device automatically asserts error flags if attempted concurrently.
Does the FS32K146UAT0VLQR support CAN-FD, and how many CAN-FD channels are available in the 100-pin LQFP package?
Yes, the FS32K146UAT0VLQR integrates three FlexCAN modules, all supporting CAN-FD protocol (ISO 11898-1). In the 100-pin LQFP package, all three CAN-FD channels are fully routable with dedicated TX/RX pins; no multiplexing or pin sharing is required for concurrent operation.
How does the FS32K146UAT0VLQR implement functional safety for ASIL-B compliance?
The FS32K146UAT0VLQR meets ASIL-B requirements through hardware-enforced mechanisms: ECC on flash and SRAM detects/corrects single-bit errors; system MPU enforces memory access rights per bus master; CRC module validates data integrity; dual watchdogs (WDOG and EWM) monitor software liveliness; and lockstep-capable peripherals (e.g., ADC) support redundancy checks.
What is the purpose of FlexRAM in the FS32K146UAT0VLQR, and how is it configured?
FlexRAM (4 KB) in the FS32K146UAT0VLQR is user-configurable as either general-purpose SRAM or EEPROM emulation storage. Configuration is performed at boot via FTFC register settings; when used as EEPROM, it provides wear-levelled, ECC-protected non-volatile storage without external components-ideal for calibration data retention in body control modules.
Can the FS32K146UAT0VLQR operate from a 3.3 V supply only, or does it support wider voltage ranges?
The FS32K146UAT0VLQR supports a full 2.7 V to 5.5 V supply range, unlike some derivatives (e.g., S32K142W) that require minimum 3.13 V. This wide range enables direct integration with 5 V automotive subsystems or 3.3 V logic domains without level-shifting, while maintaining specified ADC accuracy and I/O drive strength across the band.
FS32K146UAT0VLQR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 144-LQFP
- Series:
- S32K
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4F
- Core Size:
- 32-Bit Single-Core
- Speed:
- 112MHz
- Connectivity:
- CANbus, FlexIO, I2C, LINbus, SPI, UART/USART
- Peripherals:
- POR, PWM, WDT
- Number of I/O:
- 128
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 24x12b SAR; D/A1x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
FS32K146UAT0VLQR FAQ
1.How can I place an order for FS32K146UAT0VLQR through Aetrix?
Please submit a Request for Quotation (RFQ) for FS32K146UAT0VLQR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for FS32K146UAT0VLQR reliable?
The price and inventory of FS32K146UAT0VLQR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for FS32K146UAT0VLQR is usually 5 days.
3.What payment methods are accepted for FS32K146UAT0VLQR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for FS32K146UAT0VLQR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for FS32K146UAT0VLQR?
FS32K146UAT0VLQR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your FS32K146UAT0VLQR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for FS32K146UAT0VLQR?
For technical support, including FS32K146UAT0VLQR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your FS32K146UAT0VLQR requirements.
6.How does Aetrix verify that FS32K146UAT0VLQR is sourced from the original manufacturer or authorized distributors?
All FS32K146UAT0VLQR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that FS32K146UAT0VLQR meets industry standards.
7.What is the process for return or replacement of FS32K146UAT0VLQR?
All FS32K146UAT0VLQR units undergo pre-shipment inspection (PSI). If there is an issue with FS32K146UAT0VLQR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The FS32K146UAT0VLQR part is unused and in its original packaging.
Return procedure for FS32K146UAT0VLQR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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