NXP Semiconductors FS32R372SBK0MMVT

Overview

FS32R372SBK0MMVT from NXP Semiconductors is a dual-core automotive radar microcontroller featuring two Power Architecture e200z7 32-bit CPUs running at 240 MHz, 1.3 MB on-chip flash with ECC, and 1 MB SRAM with ECC. It integrates Signal Processing Toolbox (SPT) v2.5 for radar signal acceleration, MIPICSI2 interface (2 lanes, 1 Gbps/lane) for external radar ADCs, and functional safety support for ASIL-B applications in automotive ADAS systems.

For engineers reviewing the FS32R372SBK0MMVT datasheet, FS32R372SBK0MMVT pinout, FS32R372SBK0MMVT application, or FS32R372SBK0MMVT equivalent, this page delivers verified technical context, validated package mapping (257-pin MAPBGA), confirmed radar-specific peripherals (SPT, CTE, MIPI CSI-2), safety architecture (FCCU, MEMU, STCU2), and real-world selection guidance against comparable radar MCUs.

Technical Context

The FS32R372SBK0MMVT implements a dual-issue Harvard architecture with 16 KB instruction and 16 KB data caches per core, 64 KB DTCM, and e2eECC across flash, SRAM, crossbar, and peripherals. Its radar processing subsystem includes SPT v2.5 with FFT/sequencing engines, Cross Triggering Engine (CTE) for sub-cycle timing synchronization, and MIPI CSI-2 Rx supporting 2-lane high-speed acquisition from external radar ADCs.

Safety mechanisms include Fault Collection and Control Unit (FCCU), Memory Error Management Unit (MEMU), safe eDMA with 32 channels, Self-Test Control Unit (STCU2), and dual-system PLL with low-jitter SDPLL - all enabling end-to-end ASIL-B compliance per ISO 26262 SEooC requirements.

Key Specifications

Pinout & Package

FS32R372SBK0MMVT is housed in a 257-ball MAPBGA package (10 mm × 10 mm, 0.8 mm pitch), optimized for automotive radar ECU layouts with thermal and signal integrity constraints. Pin assignments follow NXP's standardized SIUL2-based I/O mapping, with dedicated power domains (VDD_HV_IO, VDD_LV_IO, VDD_LV_DPHY) and safety-critical signal routing (FCCU, STCU2, MEMU interfaces).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar radar microcontroller applications.

Compared with S32R274MV1A and MPC5775K, FS32R372SBK0MMVT uniquely balances compact 10 mm × 10 mm packaging, MIPI CSI-2 compatibility for modern radar ADCs, and production-ready ASIL-B certification - making it optimal for space-constrained, high-volume 77 GHz radar ECUs.

Availability

FS32R372SBK0MMVT is available at Aetrix Electronics and suitable for automotive radar ECUs, ADAS sensor fusion nodes, radar development platforms, and zonal gateways requiring stable component supply, long-term automotive qualification, and ASIL-B functional safety compliance.

Supply support for FS32R372SBK0MMVT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in radar processing and functional safety.

The S32R series is NXP's dedicated automotive radar MCU product line, designed specifically for 77/79 GHz radar signal processing, sensor fusion, and ASIL-B/D safety-critical ADAS control in compact, thermally efficient packages.

FAQ

What is the maximum operating frequency of the FS32R372SBK0MMVT CPU cores?

The FS32R372SBK0MMVT features two Power Architecture e200z7 32-bit CPU cores, each operating at a maximum frequency of 240 MHz. This performance level is sustained under full-load conditions at junction temperatures up to +150 °C, with thermal management supported by the on-chip temperature sensors (TSENS_0/TSENS_1) and voltage regulation circuitry. The FS32R372SBK0MMVT maintains deterministic timing via its dual-system PLL and low-jitter SDPLL.

Does the FS32R372SBK0MMVT support MIPI CSI-2 for radar ADC interfacing?

Yes, the FS32R372SBK0MMVT includes a dedicated MIPI CSI-2 receiver supporting 2 data lanes plus 1 clock lane, with each lane capable of up to 1 Gbps. This interface is explicitly designed to connect external radar ADCs such as the TI AFE5401 or Analog Devices AD9042. The FS32R372SBK0MMVT implements full D-PHY electrical compliance per MIPI specification, including HS-RX mode and LVDS-level signaling with AC coupling requirements.

What functional safety features does the FS32R372SBK0MMVT provide for ASIL-B compliance?

The FS32R372SBK0MMVT delivers comprehensive ASIL-B support through integrated safety modules: Fault Collection and Control Unit (FCCU), Memory Error Management Unit (MEMU), Self-Test Control Unit (STCU2), Error Injection Module (EIM), Clock Monitor Unit (CMU), and on-chip voltage supervisors. All memory paths - flash, SRAM, crossbar, and peripheral registers - feature end-to-end ECC. The FS32R372SBK0MMVT is certified as ISO 26262 SEooC ASIL-B, with safety manuals and FMEDA reports available from NXP.

What is the package type and pin count of the FS32R372SBK0MMVT?

The FS32R372SBK0MMVT uses a 257-ball MAPBGA package with a 10 mm × 10 mm body size and 0.8 mm ball pitch. This compact footprint meets stringent automotive ECU space constraints while supporting thermal dissipation up to 150 °C junction temperature. The package is RoHS-compliant and lead-free, with ball composition SnAgCu. Pinout documentation is provided in Section 19 ("Package pinouts and signal descriptions") of the official S32R372 datasheet Rev. 4.

How much on-chip memory does the FS32R372SBK0MMVT include, and what protection mechanisms apply?

The FS32R372SBK0MMVT integrates 1.3 MB of on-chip code flash memory (FMC flash) and 1 MB of on-chip SRAM, both with full ECC protection. Flash includes 32 KB of emulated EEPROM and supports read-while-write (RWW) operations. SRAM is quad-ported with 6 banks, enabling concurrent access from CPU cores, SPT, and peripherals. Memory protection is enforced via per-core MPU (24 entries each) and dual SMPUs (16 region descriptors each), ensuring isolation between safety-critical and non-safety partitions in the FS32R372SBK0MMVT.