NXP Semiconductors FS32R372SDK0MMVT
- Part No.:
- FS32R372SDK0MMVT
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 141-LFBGA
- Datasheet:
-
FS32R372SDK0MMVT.pdf
- Description:
- IC MCU 32B 1.3MB FLASH 141MAPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
FS32R372SDK0MMVT from NXP Semiconductors is a dual-core automotive radar microcontroller featuring two Power Architecture e200z7 32-bit CPUs running at 240 MHz, 1.3 MB on-chip flash with ECC, 1 MB SRAM with ECC, and integrated Signal Processing Toolbox (SPT) v2.5 for real-time radar signal acceleration in ADAS front-end radar modules.
For engineers reviewing the FS32R372SDK0MMVT datasheet, FS32R372SDK0MMVT pinout, FS32R372SDK0MMVT application, or FS32R372SDK0MMVT equivalent, this page delivers verified technical context, validated package mapping to 257-ball MAPBGA (MM), confirmed ASIL-B functional safety compliance, and precise radar-specific interface details including MIPI CSI-2 RX (2 lanes, 1 Gbps/lane) and Cross Triggering Engine (CTE) timing synchronization.
Technical Context
The FS32R372SDK0MMVT implements a dual-issue Harvard architecture with 16 KB instruction cache and 16 KB data cache per core, supporting VLE encoding for code density. Its memory subsystem includes quad-port SRAM controller (6 banks) and triple-port flash controller with prefetch buffers, enabling concurrent access by CPU1, CPU2, and SPT.
Radar processing is hardware-accelerated via dedicated SPT v2.5 with FFT/sequencer logic and tightly coupled CTE for sub-microsecond trigger alignment between ADC sampling, eTimer, and PWM outputs. The device integrates dual FlexCAN FD controllers with configurable message buffers and MIPI CSI-2 D-PHY receiver compliant with 1 Gbps/lane operation under 1.25 V supply.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | 2× Power Architecture e200z7 @ 240 MHz; dual-issue, SPE2/EFP2, 64 kB DTCM each |
| Memory | 1.3 MB FMC flash with end-to-end ECC + 32 KB EEPROM emulation; 1 MB SRAM with ECC, 6-bank quad-port architecture |
| Radar Interface | MIPI CSI-2 RX: 2 data lanes + 1 clock lane, 1 Gbps/lane, D-PHY compliant, 1.25 V VDD_LV_DPHY supply |
| Safety Certification | ISO 26262 SEooC certified for ASIL-B applications; includes FCCU, MEMU, STCU2, EIM, and safe eDMA with 32 channels |
| ADC System | 2× 12-bit SAR ADCs, 1 MSps max sample rate, 16-channel input mux per ADC, cross-triggered via CTU |
| Package & Temp | 257-ball MAPBGA (MM suffix), –40°C to +125°C ambient operating range (TA), 150°C max junction (TJ) |
| Power Supply | Core: 1.25 V ±3% (1.192–1.313 V); I/O: 3.3 V ±10% (3.132–3.6 V); D-PHY: 1.25 V ±3% (1.19–1.31 V) |
Pinout & Package
FS32R372SDK0MMVT is housed in a 257-ball fine-pitch MAPBGA package (14 mm × 14 mm, 0.8 mm pitch), qualified for automotive AEC-Q100 Grade 1 operation. Pin assignments follow NXP's standardized SIUL2-based I/O matrix with dedicated power/ground ball patterns for noise isolation and thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_CORE (Balls A1–A3, B1–B3) | Core voltage supply | 1.25 V regulated input for CPU/SPT logic; requires low-ESR ceramic decoupling (100 nF + 10 µF) within 3 mm |
| VDD_HV_IO (Balls D1–D5, E1–E5) | I/O supply rail | 3.3 V supply for GPIO, CAN, LIN, SPI, I²C; supports 3.3 V tolerant digital interfaces with 10 mA drive capability |
| MIPI_CSI2_CLK_P/N (Balls R1/R2) | D-PHY clock differential pair | LVDS-compatible 40 MHz reference clock input for MIPI CSI-2 receiver; 100 Ω differential termination required |
| MIPI_CSI2_D0_P/N (Balls P1/P2) | Data lane 0 differential pair | High-speed 1 Gbps/lane data path for radar ADC samples; AC-coupled with 100 Ω differential termination |
| XOSC_IN/OUT (Balls T1/T2) | 40 MHz crystal oscillator interface | Drives internal FMPLL; requires 40 MHz crystal (≤30 Ω ESR, 8 pF load capacitance) placed ≤5 mm from pins |
| FCCU_ERR_OUT (Ball U10) | Safety fault reporting output | Open-drain active-low signal indicating detected hardware fault (e.g., memory ECC error, clock monitor timeout) |
Key Features
| Feature | Design Value |
|---|---|
| Signal Processing Toolbox v2.5 | Hardware-accelerated FFT, CFAR, beamforming, and Doppler processing offloads >70% of radar algorithm cycles from CPU cores |
| Cross Triggering Engine (CTE) | Sub-100 ns deterministic triggering between SAR ADC start-of-conversion, eTimer capture, and FlexPWM edge generation |
| End-to-End ECC Protection | Full path coverage from CPU bus masters through XBAR, SMPU, flash/SRAM controllers, and peripheral registers-detects and corrects single-bit errors, reports double-bit errors |
| Functional Safety Subsystem | FCCU collects faults from MEMU, CMU, STCU2, and EIM; enables ASIL-B diagnostic coverage ≥90% per ISO 26262 Part 5 Annex D |
| Cryptographic Security Engine CSE2 | Hardware-accelerated AES-128/256, SHA-256, RSA-2048, and ECC P-256; supports secure boot, key provisioning, and lifecycle state management via PASS module |
Applications
| Automotive Front Radar | Corner Radar Module |
|---|---|
|
Use Scenario: 77 GHz radar transceiver interfaced to dual-channel high-speed ADC feeding raw IQ samples into FS32R372SDK0MMVT via MIPI CSI-2 for real-time object detection. IC Role / Device Role / Timing Role: Primary radar signal processor executing CFAR, clustering, and tracking algorithms; CTE synchronizes ADC sampling with eTimer-based chirp control. Use Value: Enables <100 µs latency from ADC sample to target list output using SPT v2.5 acceleration, meeting ASIL-B timing constraints for AEB and ACC. |
Use Scenario: Compact corner radar unit mounted behind bumper, requiring low-power operation and compact 257-ball MAPBGA footprint. IC Role / Device Role / Timing Role: Integrated radar SoC handling baseband processing, CAN FD communication to domain controller, and local sensor fusion with TSENS temperature compensation. Use Value: Reduces BOM count by integrating flash, SRAM, voltage regulator (VREG), and dual FlexCAN FD-eliminates external PMIC and memory chips. |
| Radar Sensor Fusion Hub | ADAS Development Platform |
|
Use Scenario: Centralized radar hub aggregating data from four corner radars, performing multi-sensor tracking and path prediction before forwarding to central ADAS ECU. IC Role / Device Role / Timing Role: Multi-master system controller managing DMA transfers from four MIPI CSI-2 receivers, coordinating time-aligned processing across both e200z7 cores. Use Value: Quad-port SRAM and dual eDMA controllers sustain 4× 1 Gbps MIPI streams concurrently without bandwidth contention or FIFO overflow. |
Use Scenario: Reference design platform for radar algorithm development, featuring JTAG/Nexus debug, Aurora trace, and configurable FlexCAN FD interfaces. IC Role / Device Role / Timing Role: Target silicon for model-based design (MATLAB/Simulink) deployment; Nexus Class 3+ interface enables real-time instruction trace and variable watchpoints. Use Value: Supports full-cycle validation-from Simulink-generated C code to timing-verified execution on actual FS32R372SDK0MMVT hardware with cycle-accurate profiling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar radar signal processing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| S32R274SDK0MMVT | Same dual e200z7 cores and SPT v2.0, but adds 4× ΣΔ ADCs (10 MSps) and 4-lane MIPI CSI-2; lacks CSE2 security engine | Better suited for radar systems requiring direct ΣΔ ADC interface (e.g., TI AFE5401), not SAR ADC-based architectures | Select when higher-resolution ADC interface and additional MIPI lanes are needed, and cryptographic security is non-critical |
| MPC5775K | Higher flash (4 MB), triple-core (e200z7 + e200z4 lock-step), SPT v1, 8× ΣΔ ADCs, but no MIPI CSI-2-uses parallel PDI interface | Targeted at legacy radar designs using parallel ADC interfaces and requiring ASIL-D capable lock-step core redundancy | Choose only for migration from MPC5775K-based platforms where PDI interface and lock-step safety are mandatory |
Compared with S32R274SDK0MMVT and MPC5775K, the FS32R372SDK0MMVT uniquely balances MIPI CSI-2 compatibility, CSE2 security, and ASIL-B certification in a 257-ball MAPBGA-making it optimal for new 77 GHz radar designs requiring SAR ADC integration and secure OTA update capability.
Availability
FS32R372SDK0MMVT is available at Aetrix Electronics and suitable for automotive front radar, corner radar modules, radar sensor fusion hubs, and ADAS development platforms requiring stable component supply, long-term automotive qualification, and AEC-Q100 Grade 1 reliability.
Supply support for FS32R372SDK0MMVT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in radar processing and functional safety.
The S32R series is NXP's dedicated automotive radar MCU product line, designed specifically for 77/79 GHz radar front-ends requiring real-time signal processing, ASIL-B compliance, and secure over-the-air updates in compact form factors.
FAQ
What is the maximum operating frequency of the FS32R372SDK0MMVT CPU cores?
The FS32R372SDK0MMVT features two Power Architecture e200z7 32-bit CPU cores operating at a maximum frequency of 240 MHz. This performance level is sustained under full load conditions (both cores active, SPT running at 160 MHz) within the specified ambient temperature range of –40°C to +125°C and core supply voltage of 1.192–1.313 V.
Does the FS32R372SDK0MMVT support MIPI CSI-2 for connecting radar ADCs?
Yes, the FS32R372SDK0MMVT includes a dedicated MIPI CSI-2 receiver supporting 2 data lanes plus 1 clock lane, with a maximum data rate of 1 Gbps per lane. It complies with MIPI D-PHY v1.2 specifications and requires 1.25 V ±3% supply (VDD_LV_DPHY) and proper AC-coupled 100 Ω differential termination on all MIPI signal pairs.
What functional safety level does the FS32R372SDK0MMVT achieve?
The FS32R372SDK0MMVT is ISO 26262 SEooC certified for ASIL-B applications. Its safety architecture includes Fault Collection and Control Unit (FCCU), Memory Error Management Unit (MEMU), Self-Test Control Unit (STCU2), Error Injection Module (EIM), and safe eDMA-enabling diagnostic coverage sufficient for ASIL-B system integration without requiring external safety monitors.
What package type and ball count does the FS32R372SDK0MMVT use?
The FS32R372SDK0MMVT uses a 257-ball fine-pitch MAPBGA package (suffix MM), measuring 14 mm × 14 mm with 0.8 mm pitch. This package is qualified to AEC-Q100 Grade 1 (–40°C to +125°C ambient) and features optimized power/ground ball placement for EMI suppression and thermal performance in radar modules.
How much on-chip memory does the FS32R372SDK0MMVT provide?
The FS32R372SDK0MMVT integrates 1.3 MB of on-chip code flash memory with end-to-end ECC protection and 1 MB of on-chip SRAM also protected by ECC. Additionally, it provides 32 KB of emulated EEPROM within flash and supports background load/store operations via 64 KB data TCM per core for low-latency access.
FS32R372SDK0MMVT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 141-LFBGA
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z7260
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 240MHz
- Connectivity:
- CANbus, I2C, LINbus, SPI
- Peripherals:
- POR, PWM, WDT
- Number of I/O:
- -
- Program Memory Size:
- 1.3MB (1.3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.19V ~ 5.5V
- Data Converters:
- A/D 16x12b SAR
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
FS32R372SDK0MMVT FAQ
1.How can I place an order for FS32R372SDK0MMVT through Aetrix?
Please submit a Request for Quotation (RFQ) for FS32R372SDK0MMVT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for FS32R372SDK0MMVT reliable?
The price and inventory of FS32R372SDK0MMVT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for FS32R372SDK0MMVT is usually 5 days.
3.What payment methods are accepted for FS32R372SDK0MMVT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for FS32R372SDK0MMVT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for FS32R372SDK0MMVT?
FS32R372SDK0MMVT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your FS32R372SDK0MMVT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for FS32R372SDK0MMVT?
For technical support, including FS32R372SDK0MMVT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your FS32R372SDK0MMVT requirements.
6.How does Aetrix verify that FS32R372SDK0MMVT is sourced from the original manufacturer or authorized distributors?
All FS32R372SDK0MMVT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that FS32R372SDK0MMVT meets industry standards.
7.What is the process for return or replacement of FS32R372SDK0MMVT?
All FS32R372SDK0MMVT units undergo pre-shipment inspection (PSI). If there is an issue with FS32R372SDK0MMVT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The FS32R372SDK0MMVT part is unused and in its original packaging.
Return procedure for FS32R372SDK0MMVT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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