onsemi FUSB301ATMX-SN00362
- Part No.:
- FUSB301ATMX-SN00362
- Manufacturer:
- onsemi
- Category:
- Controllers
- Package:
- -
- Datasheet:
-
FUSB301ATMX-SN00362.pdf
- Description:
- POWER SUPPLY SUPPORT CIRCUIT
- Quantity:
- Payment:

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Product details
Overview
FUSB301ATMX-SN00362 from Fairchild Semiconductor is an autonomous USB Type-C controller supporting DRP, Sink, Source, and accessory detection modes with configurable I²C address (bit 3 selectable), 3.0–5.5 V operation, ≤7.0 µA standby current, and 12-lead TMLP (1.6 mm × 1.6 mm × 0.375 mm) packaging - deployed in smartphones and ultra-portable devices for CC logic detection and dead-battery UFP support.
For engineers reviewing the FUSB301ATMX-SN00362 datasheet, pinout, applications, or equivalent options, key selection criteria include autonomous Type-C state machine execution, dual CC pin handling (CC1/CC2), VBUS presence detection with 3.7 V threshold, interrupt-driven host notification via INT_N, and support for Try.SNK/Try.SRC negotiation sequences.
Technical Context
The FUSB301ATMX-SN00362 implements a fully autonomous Type-C state machine compliant with USB Type-C Specification Revision 1.1, managing CC line detection, orientation sensing (ORIENT[1:0]), and Rd/Ra threshold comparisons (vRd-def = 0.66 V typ., vRa-SNK = 0.20 V typ.) without host CPU intervention during attach/detach events.
It integrates configurable pull-up currents (80 µA / 180 µA / 330 µA) for Source mode, dead-battery UFP operation with CC pull-down activation when VDD = 0 V, and I²C slave interface operating at up to 400 kHz with programmable 7-bit address (0x42 or 0x43 based on I2CADDR pin).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDD Range | 3.0 V to 5.5 V - Supports direct connection to common system rails including 3.3 V and 5 V supplies. |
| Standby Current | ≤7.0 µA - Enables always-on CC monitoring in battery-powered portable systems with minimal quiescent drain. |
| CC Detection Thresholds | vRd-def = 0.66 V, vRa-SNK = 0.20 V - Precisely identifies sink attachment and Ra presence per USB Type-C spec. |
| VBUS Detection Threshold | 3.7 V - Ensures reliable VBUSOK assertion before enabling power delivery handshaking. |
| I²C Address | 0x42 or 0x43 - Configurable via I2CADDR pin to enable multi-port systems without address conflict. |
| Package | 12-Lead TMLP (1.6 mm × 1.6 mm × 0.375 mm) - Ultra-thin footprint compatible with space-constrained mobile PCB layouts. |
| ESD Protection | 2 kV HBM on CC1/CC2/VBUS - Meets robustness requirements for exposed USB-C connector interfaces. |
Pinout & Package
12-lead Ultra-thin Molded Leadless Package (TMLP), 1.6 mm × 1.6 mm × 0.375 mm, bottom-exposed thermal pad (no internal thermal slug), JEDEC-compliant land pattern per MKT-TMLP12Arev1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ID | Open-drain output | Indicates detected role (Sink = LOW, Hi-Z = not detected); interfaces directly with USB 2.0 input on host processor. |
| SDA | I²C data (open-drain) | Bi-directional serial data line for register read/write; requires external pull-up to VDD. |
| SCL | I²C clock (input) | Master-generated clock synchronizing all I²C transactions; supports Fast Mode (400 kHz). |
| VDD | Power supply | Main supply input (3.0–5.5 V); powers internal logic, comparators, and CC switches. |
| CC2 | Configuration Channel I/O | Active bidirectional pin for Type-C cable orientation detection and Rd/Ra sensing on CC2 line. |
| VBUS | Input | Detects presence of VBUS (3.7–21 V range); triggers VBUSOK status and enables power-path control logic. |
| CC1 | Configuration Channel I/O | Active bidirectional pin for Type-C cable orientation detection and Rd/Ra sensing on CC1 line. |
| INT_N | Open-drain interrupt output | Active-low signal notifying host processor of attach/detach/accessory events; requires external pull-up. |
| GND | Ground reference | Primary analog and digital ground return; must be low-impedance connection to system GND plane. |
| I2CADDR | Address configuration input | Logic level sets bit 3 of I²C slave address: LOW → 0x42, HIGH → 0x43. |
| NC1, NC2 | No-connect | Unused pins; recommended to tie to GND or leave floating per layout constraints. |
Key Features
| Feature | Design Value |
|---|---|
| Autonomous Type-C State Machine | Executes full USB Type-C 1.1 attach/detach/role-swap logic without host firmware polling or timing-critical intervention. |
| Dead-Battery UFP Support | Activates internal Rd pull-down on CC line when VDD = 0 V, enabling VBUS turn-on by source even with no system power. |
| DRP Toggle Timing Control | Four programmable DRP toggle intervals (20–70 ms) via DRPTOGGLE bits to optimize dual-role negotiation latency and power trade-offs. |
| Configurable Source Current Modes | Selects 80 µA (default), 180 µA (1.5 A), or 330 µA (3 A) CC pull-up via HOST_CUR[1:0] register bits for precise current advertisement. |
| Interrupt-Driven Host Interface | INT_N asserts on attach/detach/accessory change; maskable per-event via MASK register to reduce host wakeups. |
Applications
| Smartphone Charging Port | Tablet Dual-Role Docking |
|---|---|
Use Scenario: USB-C port on smartphone supporting both charging (Sink) and peripheral connection (Source/DRP) with audio/debug accessory detection. IC Role / Device Role / Timing Role: Autonomous CC logic controller managing orientation detection, VBUS monitoring, and role negotiation independent of AP boot state. Use Value: Enables dead-battery charging and seamless accessory plug-in without AP involvement, reducing system power and firmware complexity. |
Use Scenario: Tablet connects to USB-C dock for display output, data transfer, and power delivery while maintaining local USB 2.0 connectivity. IC Role / Device Role / Timing Role: DRP controller toggling between Sink and Source states with accessory support, coordinating with PMIC and USB 3.1 switch (e.g., FUSB340). Use Value: Eliminates need for dedicated USB-C PHY firmware stack; handles Try.SNK/Try.SRC sequences and BC_LVL current detection automatically. |
| Notebook Power Delivery Negotiation | Ultra-Portable Device CC Monitoring |
Use Scenario: Thin-and-light notebook negotiates 45 W PD contract with USB-C charger while detecting whether connected device is UFP, DFP, or debug accessory. IC Role / Device Role / Timing Role: Source-mode controller advertising 330 µA pull-up, validating Ra presence, and asserting VBUSOK only after stable CC handshake. Use Value: Guarantees compliance with USB PD 2.0 sink initiation requirements using hardware-level timing (tCCDebounce = 75 ms typ. for Sink). |
Use Scenario: Wearable or IoT device with USB-C port requires always-on, ultra-low-power CC monitoring for firmware update or diagnostics via cable attach. IC Role / Device Role / Timing Role: Standby-mode Sink controller consuming ≤7.0 µA while continuously sampling CC1/CC2 for Ra/Rd transitions and orientation changes. Use Value: Achieves <10 µA average system current during cable-detection-only operation, extending battery life in maintenance-free deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB Type-C controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STUSB4500QTR | Integrated VBUS discharge path; supports USB PD 3.0; 10-pin QFN vs. 12-pin TMLP | Requires PD-aware host firmware; lacks dead-battery UFP support in hardware | Choose for PD 3.0 systems needing integrated discharge; avoid if autonomous dead-battery operation is required. |
| TUSB320LAIAR | I²C address fixed at 0x48; no DRP toggle timing control; supports only Sink/Source (no accessory modes) | Limited to basic Type-C detection; no DEBUGACC/AUDIOACC identification or DRP+ACC mode | Choose for cost-sensitive single-role designs; avoid if accessory detection or flexible DRP timing is needed. |
Compared with STUSB4500QTR and TUSB320LAIAR, the FUSB301ATMX-SN00362 uniquely delivers hardware-based dead-battery UFP support, programmable DRP toggle timing, and accessory-class identification - making it optimal for autonomous, low-power mobile endpoints where host CPU involvement must be minimized.
Availability
FUSB301ATMX-SN00362 is available at Aetrix Electronics and suitable for smartphones, tablets, and ultra-portable devices requiring stable component supply, long-term lifecycle assurance, and guaranteed traceability for consumer electronics production.
Supply support for FUSB301ATMX-SN00362 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Fairchild Semiconductor was a leading designer of high-performance analog and power ICs, acquired by ON Semiconductor in 2016; its legacy USB-C controllers remain widely deployed in mobile infrastructure.
The FUSB301A product line was engineered specifically for autonomous, low-power USB Type-C port management in space- and energy-constrained portable devices - prioritizing hardware-offloaded state machine execution over host CPU dependency.
FAQ
What is the function of the I2CADDR pin on the FUSB301ATMX-SN00362?
The I2CADDR pin on the FUSB301ATMX-SN00362 selects bit 3 of the 7-bit I²C slave address: pulled LOW for 0x42, HIGH for 0x43. This allows two FUSB301ATMX-SN00362 devices to coexist on the same I²C bus without address collision - essential for multi-port systems like dual-USB-C laptops or docking stations. The pin is sampled at power-up and latched; changing it mid-operation has no effect.
Does the FUSB301ATMX-SN00362 support USB Power Delivery (PD) protocol negotiation?
No, the FUSB301ATMX-SN00362 does not implement USB PD protocol negotiation. It handles only USB Type-C physical layer functions: CC line detection, orientation sensing, Rd/Ra threshold comparison, VBUS monitoring, and autonomous state machine control per USB Type-C Spec 1.1. PD communication requires a separate PD controller (e.g., FUSB302B or CYPD3125) paired with the FUSB301ATMX-SN00362 for complete solution.
How does dead-battery operation work on the FUSB301ATMX-SN00362?
When VDD = 0 V and a USB-C source is attached, the FUSB301ATMX-SN00362 uses residual voltage from the source's CC pull-up to activate its internal Rd pull-down on the connected CC line. This pulls the CC voltage into the source's detectable range (vRa-SRCdef = 0.20 V), triggering VBUS turn-on. Once VBUS rises above 3.7 V, the FUSB301ATMX-SN00362 powers up and assumes normal operation - enabling true zero-power cable detection.
What are the supported modes of operation for the FUSB301ATMX-SN00362?
The FUSB301ATMX-SN00362 supports six operational modes configured via the MODES register (0x02): Sink, Source, DRP, Sink+ACC, Source+ACC, and DRP+ACC. Each mode defines behavior for CC line monitoring, VBUS response, and accessory detection. Mode selection is static at initialization; dynamic switching (e.g., DRP toggle timing) is controlled separately via DRPTOGGLE bits in the CONTROL register (0x03).
Can the FUSB301ATMX-SN00362 be used in automotive applications?
No - the FUSB301ATMX-SN00362 is specified for commercial temperature range (−40°C to +85°C) and is not qualified for automotive use per AEC-Q100. Fairchild explicitly restricted its use to non-safety-critical applications in the datasheet's "Authorized Use" section, excluding automotive, aerospace, and life-critical medical equipment unless approved in writing. For automotive USB-C ports, AEC-Q100-qualified alternatives such as the TUSB564 or USB3343 are required.
FUSB301ATMX-SN00362 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- -
- Programmable:
- Not Verified
- Protocol:
- -
- Function:
- -
- Interface:
- -
- Standards:
- -
- Voltage - Supply:
- -
- Current - Supply:
- -
- Operating Temperature:
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- Supplier Device Package:
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FUSB301ATMX-SN00362 FAQ
1.How can I place an order for FUSB301ATMX-SN00362 through Aetrix?
Please submit a Request for Quotation (RFQ) for FUSB301ATMX-SN00362 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for FUSB301ATMX-SN00362 reliable?
The price and inventory of FUSB301ATMX-SN00362 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for FUSB301ATMX-SN00362 is usually 5 days.
3.What payment methods are accepted for FUSB301ATMX-SN00362?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for FUSB301ATMX-SN00362 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for FUSB301ATMX-SN00362?
FUSB301ATMX-SN00362 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your FUSB301ATMX-SN00362 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for FUSB301ATMX-SN00362?
For technical support, including FUSB301ATMX-SN00362 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your FUSB301ATMX-SN00362 requirements.
6.How does Aetrix verify that FUSB301ATMX-SN00362 is sourced from the original manufacturer or authorized distributors?
All FUSB301ATMX-SN00362 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that FUSB301ATMX-SN00362 meets industry standards.
7.What is the process for return or replacement of FUSB301ATMX-SN00362?
All FUSB301ATMX-SN00362 units undergo pre-shipment inspection (PSI). If there is an issue with FUSB301ATMX-SN00362, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The FUSB301ATMX-SN00362 part is unused and in its original packaging.
Return procedure for FUSB301ATMX-SN00362:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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