Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Translators, Level Shifters

NXP Semiconductors GTL2007PW,118

Name: GTL2007PW,118
Brand: NXP Semiconductors
SKU: GTL2007PW,118
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: GTL2007PW,118

Manufacturer:: NXP Semiconductors

Category:: Translators, Level Shifters

Package:

Datasheet:: GTL2007PW,118.pdf

Description:: IC TRANSLATOR UNIDIR 28TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,928

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

GTL2007PW,118 from NXP Semiconductors is a 12-bit bidirectional GTL-to-LVTTL translator with dual enable-controlled error output disable for Xeon processor platform health monitoring. It operates across 3.0–3.6 V supply, supports GTL/GTL+/GTL− signal levels (VTT = 1.1–1.2 V, Vref = 0.64–1.1 V), and integrates series-terminated 30 Ω LVTTL outputs for clean signal integrity in CPU power-good coordination circuits.

For engineers reviewing the GTL2007PW,118 datasheet, GTL2007PW,118 pinout, GTL2007PW,118 application, or GTL2007PW,118 equivalent, key selection criteria include its dual EN-controlled glitch suppression on 7BO1/7BO2 outputs, 100–350 ns propagation delay for PROCHOT/NMI paths, open-drain LVTTL I/O support (5A/6A/11A), and TSSOP28 package compatibility with high-density server motherboard layouts.

Technical Context

The GTL2007PW,118 implements two independent enable-controlled translation channels: EN1 gates 1AO/2AO and 5A connectivity to 5BI, while EN2 gates 3AO/4AO and 6A connectivity to 6BI - each with built-in delay to suppress LOW glitches during power-down transients. Its architecture supports simultaneous GTL input sampling (e.g., 1BI–4BI, 9BI, 11BI) and LVTTL output driving (e.g., 1AO–4AO, 9AO, 11BO) with separate VREF (Pin 1) and VCC (Pin 28) rails.

It delivers deterministic timing for critical platform signals: 11BI→11BO propagation delay ranges 2–21 ns; 5BI→7BO1/6BI→7BO2 spans 4–350 ns depending on transition type; and EN1/EN2→nAO response is 2–10 ns. All GTL outputs (e.g., 7BO1, 10BO1) are actively driven, while LVTTL open-drain I/Os require external pull-ups per JEDEC-compliant SMI/PROCHOT/NMI protocols.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage	3.0 V to 3.6 V - ensures compatibility with standard 3.3 V LVTTL logic domains and avoids overvoltage stress on non-5 V-tolerant I/Os.
VREF Range	0.64 V to 1.1 V - supports evolving GTL reference requirements down to 0.66 V minimum, enabling forward compatibility with future VTT scaling (e.g., 0.63 × VTT).
Propagation Delay (nBI → nAO)	2–10 ns typical - guarantees sub-10 ns latency for real-time CPU error reporting (IERR_L, THRMTRIP_L) to platform health management logic.
Propagation Delay (5BI → 7BO1)	4–350 ns - includes intentional delay to prevent false PROCHOT_L assertion during uncontrolled power-down events like VRD overload or thermal trip.
LVTTL Output Series Termination	30 Ω integrated - eliminates need for discrete series resistors on 1AO–4AO/9AO outputs, reducing BOM count and PCB area in high-speed CPU interface routing.
ESD Protection	2000 V HBM / 200 V MM / 1000 V CDM - meets industrial-grade robustness requirements for handling during server board assembly and field maintenance.
Operating Temperature	−40 °C to +85 °C - validated for continuous operation in enterprise server chassis with localized hot spots near CPU VRMs and memory modules.

Pinout & Package

TSSOP28 (SOT361-1) package: plastic thin shrink small outline, 28 leads, 4.4 mm body width, 0.65 mm pitch - optimized for automated placement and reflow soldering on dense server motherboard layers.

Pin/Terminal	Circuit Role	Design Meaning
VREF (1)	GTL reference voltage input	Defines GTL switching threshold (Vref ± 0.05 V); must be decoupled locally to maintain noise immunity for 11BI/9BI/4BI inputs.
1AO–4AO, 9AO (2–4, 10–11, 15)	LVTTL outputs	Actively driven, 30 Ω series-terminated; connect directly to South Bridge or PHM logic without external resistors.
5A/6A/11A (5, 6, 8)	Open-drain LVTTL I/O	Require external pull-up (e.g., 1.2–1.5 kΩ to VCC) for SMI/PROCHOT/NMI bidirectional signaling per Intel platform specs.
EN1/EN2 (6, 23)	Enable inputs	Synchronize translation enable with VRD power-good signals; low state disables 1AO/2AO/5A (EN1) or 3AO/4AO/6A (EN2) to mask transient errors.
7BO1/7BO2 (25, 24)	GTL error outputs	Driven HIGH when PROCHOT_L asserted; include internal delay to suppress glitches caused by 5A/6A turn-on lag relative to 5BI/6BI transitions.
10AI1/10AI2 (12–13)	LVTTL inputs	Accept SMI_L signals from CPUs; paired with 9BI to generate active-HIGH 10BO1/10BO2 outputs for South Bridge SMI_L buffering.

Key Features

Feature	Design Value
Dual independent enable control (EN1/EN2)	Allows selective masking of CPU1 and CPU2 error paths (IERR_L, THRMTRIP_L) without affecting shared GTL bus integrity.
Integrated 30 Ω series termination on LVTTL outputs	Reduces signal reflections on 100+ mm traces between CPU socket and PHM IC, eliminating six discrete 30 Ω resistors per device.
GTL input hysteresis and Vref flexibility (0.64–1.1 V)	Accommodates VTT drift across temperature/voltage corners and supports migration to lower GTL thresholds in next-gen Xeon platforms.
Glitch-suppressed 7BO1/7BO2 outputs	Prevents false PROCHOT_L assertion during asymmetric power sequencing - critical for reliable thermal throttling in dual-CPU systems.
JEDEC-compliant open-drain LVTTL I/O (5A/6A/11A)	Enables direct connection to Intel VRD power-good and NMI lines without level-shifting or additional buffer logic.

Applications

CPU Thermal Trip Monitoring	Platform Health Management Interface
Use Scenario: Detecting and relaying CPU thermal trip events (THRMTRIP_L) from dual Xeon processors to platform health controller. IC Role / Device Role / Timing Role: Translates GTL-level THRMTRIP_L signals from CPU die to LVTTL-compatible inputs for South Bridge or BMC, with EN1/EN2 enabling selective masking during graceful shutdown. Use Value: Prevents spurious system reset by suppressing false THRMTRIP_L assertions during VRD power collapse, using built-in 100 ns delay on 7BO1/7BO2 outputs.	Use Scenario: Aggregating and conditioning multiple CPU status signals (IERR_L, FORCEPR_L, PROCHOT_L) for centralized platform health monitoring. IC Role / Device Role / Timing Role: Acts as a signal conditioner and protocol adapter between GTL CPU outputs and LVTTL PHM logic, supporting concurrent SMI/NMI/PROCHOT paths. Use Value: Reduces PHM ASIC pin count by consolidating 12 GTL-to-LVTTL translations into one TSSOP28 device, with dedicated EN controls per CPU domain.
Server Power Supply Coordination	Dual-CPU SMI/NMI Buffering
Use Scenario: Coordinating power-good sequencing between dual CPU VRDs and main system power supply via FORCEPR_L and DISABLE_L signals. IC Role / Device Role / Timing Role: Provides bidirectional translation between GTL FORCEPR_L (CPU side) and LVTTL DISABLE_L (PHM side), with EN1/EN2 tied to individual VRD power-good outputs. Use Value: Enables independent CPU power-down sequencing - e.g., disabling CPU2 while keeping CPU1 active - without requiring custom FPGA logic.	Use Scenario: Buffering and synchronizing SMI_L and NMI_L interrupts from two Xeon CPUs to a single South Bridge interrupt input. IC Role / Device Role / Timing Role: Converts GTL SMI/NMI inputs (9BI, 11BI) to LVTTL outputs (10BO1/10BO2, 11BO) with precise timing alignment and open-drain drive capability. Use Value: Eliminates race conditions in multi-CPU interrupt arbitration by ensuring deterministic 2–13 ns propagation delay and glitch-free edge alignment.

CPU Thermal Trip Monitoring

Platform Health Management Interface

Use Scenario: Detecting and relaying CPU thermal trip events (THRMTRIP_L) from dual Xeon processors to platform health controller.

IC Role / Device Role / Timing Role: Translates GTL-level THRMTRIP_L signals from CPU die to LVTTL-compatible inputs for South Bridge or BMC, with EN1/EN2 enabling selective masking during graceful shutdown.

Use Value: Prevents spurious system reset by suppressing false THRMTRIP_L assertions during VRD power collapse, using built-in 100 ns delay on 7BO1/7BO2 outputs.

Use Scenario: Aggregating and conditioning multiple CPU status signals (IERR_L, FORCEPR_L, PROCHOT_L) for centralized platform health monitoring.

IC Role / Device Role / Timing Role: Acts as a signal conditioner and protocol adapter between GTL CPU outputs and LVTTL PHM logic, supporting concurrent SMI/NMI/PROCHOT paths.

Use Value: Reduces PHM ASIC pin count by consolidating 12 GTL-to-LVTTL translations into one TSSOP28 device, with dedicated EN controls per CPU domain.

Server Power Supply Coordination

Dual-CPU SMI/NMI Buffering

Use Scenario: Coordinating power-good sequencing between dual CPU VRDs and main system power supply via FORCEPR_L and DISABLE_L signals.

IC Role / Device Role / Timing Role: Provides bidirectional translation between GTL FORCEPR_L (CPU side) and LVTTL DISABLE_L (PHM side), with EN1/EN2 tied to individual VRD power-good outputs.

Use Value: Enables independent CPU power-down sequencing - e.g., disabling CPU2 while keeping CPU1 active - without requiring custom FPGA logic.

Use Scenario: Buffering and synchronizing SMI_L and NMI_L interrupts from two Xeon CPUs to a single South Bridge interrupt input.

IC Role / Device Role / Timing Role: Converts GTL SMI/NMI inputs (9BI, 11BI) to LVTTL outputs (10BO1/10BO2, 11BO) with precise timing alignment and open-drain drive capability.

Use Value: Eliminates race conditions in multi-CPU interrupt arbitration by ensuring deterministic 2–13 ns propagation delay and glitch-free edge alignment.

Equivalent & Alternatives

The following parts are listed as comparable options for similar GTL-to-LVTTL translation applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
NXP GTL2006PW,118	No EN1/EN2 enable inputs; fixed translation without error-output disable capability.	Cannot suppress false PROCHOT_L/IERR_L during uncontrolled power-down; requires external gating logic for platform health masking.	Select GTL2007PW,118 when dual-CPU thermal/power event isolation is required; GTL2006PW,118 suits simpler single-CPU or always-active translation roles.
TI SN74GTL16612DGGR	16-bit, 3.3 V only, no VREF adjustment; lacks dedicated PROCHOT/NMI timing delay blocks.	Supports higher channel count but cannot replicate GTL2007PW,118's glitch-suppressed 7BO1/7BO2 outputs or Vref-scaling for future GTL variants.	Choose GTL2007PW,118 for Intel Xeon platform compliance and thermal-event reliability; SN74GTL16612DGGR fits generic high-pin-count GTL buffering where delay control is not critical.

Compared with GTL2006PW,118, GTL2007PW,118 adds essential enable-controlled error suppression for server RAS; versus SN74GTL16612DGGR, it provides tighter timing control for PROCHOT/NMI paths and adaptive Vref support - both critical for Xeon platform health management integration.

Availability

GTL2007PW,118 is available at Aetrix Electronics and suitable for enterprise server motherboard design, CPU VRD coordination, and platform health management subsystems requiring stable component supply across extended product lifecycles.

Supply support for GTL2007PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and communication infrastructure markets.

The GTL2007PW,118 belongs to NXP's high-speed interface translator product line, engineered specifically for Intel Xeon processor platform interoperability - addressing GTL/LVTTL voltage translation, power-good synchronization, and thermal event reliability in dual-CPU server architectures.

FAQ

What is the primary function of the GTL2007PW,118 in a dual-Xeon server platform?

The GTL2007PW,118 serves as a 12-bit GTL-to-LVTTL translator that bridges Xeon processor GTL signals (e.g., IERR_L, THRMTRIP_L, PROCHOT_L) with LVTTL-based platform health management and South Bridge logic. Its dual EN1/EN2 inputs allow independent masking of CPU1 and CPU2 error paths during power transitions, preventing false alerts to the monitoring agent - a core requirement in enterprise server RAS design. The GTL2007PW,118 enables deterministic, low-latency signal conditioning without external components.

How does the GTL2007PW,118 handle false error conditions during unexpected power-down events?

The GTL2007PW,118 uses EN1 and EN2 inputs to disable its error outputs (7BO1/7BO2) when system power integrity is compromised - such as during VRD overload, CPU thermal trip, or uncontrolled shutdown. Each enable line includes an internal delay that prevents LOW glitches on 7BO1/7BO2 when 5BI/6BI rise before 5A/6A, ensuring PROCHOT_L remains stable. This behavior is explicitly characterized in the datasheet's Table 8 (PROCHOT signals) and Figure 7 waveforms. The GTL2007PW,118 thus maintains platform health accuracy under fault conditions.

What are the voltage requirements for GTL2007PW,118 VREF and VTT, and why is VREF adjustable down to 0.66 V?

The GTL2007PW,118 requires VREF between 0.64 V and 1.1 V (typical 0.73–0.76 V) and VTT between 1.1 V and 1.2 V. The 0.66 V minimum VREF supports future GTL specifications where Vref scales to 0.63 × VTT - for example, 0.693 V at VTT = 1.1 V. This headroom ensures backward compatibility with existing Xeon platforms while enabling forward compatibility with next-generation GTL voltage plans. The GTL2007PW,118's characterization confirms minimal DC/AC performance variation across this full Vref range.

Can GTL2007PW,118 LVTTL I/O pins (5A, 6A, 11A) be used without external pull-up resistors?

No - the GTL2007PW,118's 5A, 6A, and 11A pins are open-drain LVTTL I/Os and require external pull-up resistors (typically 1.2–1.5 kΩ to VCC) to establish HIGH-state logic levels for SMI, PROCHOT, and NMI signaling. This matches Intel VRD and platform specification requirements. The GTL2007PW,118 datasheet explicitly states these pins operate as open-drain terminals driven LOW by other drivers (Table 3, Note [2]), and Figure 3 shows 1.5 kΩ pull-ups in the typical application circuit. Using them without pull-ups would result in undefined or floating states.

What package type and footprint does GTL2007PW,118 use, and what are its soldering requirements?

The GTL2007PW,118 is packaged in TSSOP28 (SOT361-1): 28-lead, 4.4 mm body width, 0.65 mm pitch. It is designed for reflow soldering per J-STD-020C - compatible with both SnPb (peak 220–235 °C) and lead-free (peak 245–260 °C) profiles depending on package thickness and volume. Moisture sensitivity level (MSL) compliance must be observed per packing labeling. The GTL2007PW,118's thin profile and fine pitch make wave soldering unsuitable; reflow is the only recommended process, with attention to preheat ramp rates and peak temperature control to avoid thermal damage.

GTL2007PW,118 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: -

Package/Case:

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Translator Type:: Mixed Signal

Channel Type:: Unidirectional

Number of Circuits:: 1

Channels per Circuit:: 12

Voltage - VCCA:: -

Voltage - VCCB:: -

Input Signal:: GTL

Output Signal:: LVTTL

Output Type:: Open Drain

Data Rate:: -

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Features:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 28-TSSOP (0.173", 4.40mm Width)

GTL2007PW,118 FAQ

1.How can I place an order for GTL2007PW,118 through Aetrix?

Please submit a Request for Quotation (RFQ) for GTL2007PW,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for GTL2007PW,118 reliable?

The price and inventory of GTL2007PW,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for GTL2007PW,118 is usually 5 days.

3.What payment methods are accepted for GTL2007PW,118?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for GTL2007PW,118 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for GTL2007PW,118?

GTL2007PW,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your GTL2007PW,118 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for GTL2007PW,118?

For technical support, including GTL2007PW,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your GTL2007PW,118 requirements.

6.How does Aetrix verify that GTL2007PW,118 is sourced from the original manufacturer or authorized distributors?

All GTL2007PW,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that GTL2007PW,118 meets industry standards.

7.What is the process for return or replacement of GTL2007PW,118?

All GTL2007PW,118 units undergo pre-shipment inspection (PSI). If there is an issue with GTL2007PW,118, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The GTL2007PW,118 part is unused and in its original packaging.

Return procedure for GTL2007PW,118:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…