NXP Semiconductors GTL2009PW,118

Overview

GTL2009PW,118 from NXP Semiconductors (formerly Philips Semiconductors) is a 3-bit GTL Front-Side Bus frequency comparator IC designed for dual-processor Intel Xeon platforms (Nocona/Dempsey/Blackford). It compares two 3-bit GTL-encoded FSB frequency inputs, selects the lower common frequency, and outputs it as GTL-level signals (BO1–BO3) while providing LVTTL status outputs (AO1/AO2) indicating slot occupancy and frequency equality. It operates from 3.0 V to 3.6 V supply and supports VREF down to 0.66 V for compatibility with evolving GTL termination voltages.

For engineers reviewing the GTL2009PW,118 datasheet, GTL2009PW,118 pinout, GTL2009PW,118 application in dual-Xeon FSB synchronization, or GTL2009PW,118 equivalent for legacy server platform design-in, this device delivers deterministic bus frequency arbitration with sub-30 ns propagation delay, robust ESD protection (>2000 V HBM), and TSSOP16 packaging optimized for high-density motherboard layouts.

Technical Context

The GTL2009PW,118 implements a dedicated hardware comparator logic block that evaluates two independent 3-bit GTL-encoded FSB settings (A and B ports) and asserts the lowest valid frequency on three GTL outputs. Its internal static 0.6 V reference comparator triggers output switching from default 100 MHz only after VREF crosses threshold - ensuring stable initialization before FSB negotiation begins.

It features separate input domains: LVTTL-compatible A-port inputs (1AI, 2AI, AO1, AO2) for slot occupancy signaling and GTL-compatible B-port inputs (1BI1–1BI3, 2BI1–2BI3) for frequency encoding. Propagation delays are asymmetric across paths: BI→BO worst-case is 30 ns, while AI→AO is ≤16 ns, reflecting its role as a control-status co-processor rather than a data path element.

Key Specifications

Pinout & Package

TSSOP16 package (SOT403-1): plastic thin shrink small outline, 16 leads, 4.4 mm body width, 0.65 mm lead pitch - optimized for automated placement and reflow soldering on dense server PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FSB frequency arbitration applications.

Compared with GTL2007PW,118, the GTL2009PW,118 offers deterministic status output behavior without enable control overhead; compared with GTL2006PW,118, it adds essential hardware-based FSB arbitration logic required for dual-processor coherence - making it the minimal viable solution for Nocona/Dempsey dual-socket designs.

Availability

GTL2009PW,118 is available at Aetrix Electronics and suitable for Intel Xeon server motherboard design, dual-processor platform validation, and legacy enterprise workstation upgrades requiring stable component supply and long-term lifecycle support.

Supply support for GTL2009PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company formed from the spin-off of Philips Semiconductors, specializing in secure connectivity solutions for automotive, industrial, and communication markets.

The GTL2009PW,118 belongs to NXP's legacy server platform companion IC portfolio, specifically engineered to address deterministic FSB arbitration requirements in dual-socket Intel Xeon systems prior to integrated memory controller adoption.

FAQ

What is the default FSB frequency output by the GTL2009PW,118 at power-up?

The GTL2009PW,118 outputs a default FSB frequency of 100 MHz (encoded as 101 on BO1–BO3) upon power-up when VDD exceeds 1.5 V. This default remains active until the VREF input crosses the internal 0.6 V comparator threshold, at which point the computed common FSB frequency replaces the default value. The 100 MHz default ensures safe, known bus initialization before full platform negotiation begins.

How does the GTL2009PW,118 determine the common FSB frequency when both processor slots are occupied?

When both processor slots are occupied, the GTL2009PW,118 compares the 3-bit GTL-encoded FSB frequency inputs from each socket (A-BSEL1–3 and B-BSEL1–3) and selects the lower frequency as the common FSB setting. The result is asserted on BO1–BO3, while AO2 indicates whether Processor A's frequency is greater than or equal to Processor B's, and AO1 signals exact equality - enabling hardware-coordinated bus speed selection without BIOS involvement.

What are the voltage level requirements for GTL inputs on the GTL2009PW,118?

The GTL inputs (1BI1–1BI3, 2BI1–2BI3) on the GTL2009PW,118 require VTT termination at either 1.1 V (Dempsey/Blackford) or 1.2 V (Nocona), with corresponding VREF nominal values of 0.73 V or 0.76 V. The device supports a minimum VREF of 0.66 V to accommodate future VTT reductions down to 0.63 × VTT, ensuring forward compatibility across multiple Xeon generations.

Can the GTL2009PW,118 be used in single-processor configurations?

Yes, the GTL2009PW,118 supports single-processor operation: when only one slot is occupied (e.g., A-occupied only), it outputs that processor's FSB frequency setting on BO1–BO3. The AO1 and AO2 outputs reflect slot occupancy status (1AI/2AI) and maintain defined logic levels per Table 8, allowing seamless integration into both single- and dual-socket motherboard designs without redesign.

What is the maximum propagation delay from GTL input to GTL output for the GTL2009PW,118?

The maximum propagation delay from GTL input to GTL output (BI to BO) for the GTL2009PW,118 is 30 ns under worst-case conditions (CL = 30 pF, VDD = 3.3 V), as specified in Table 1 of the datasheet. This delay ensures reliable FSB arbitration completion within one cycle even at 400 MHz FSB (2.5 ns period), providing sufficient timing margin for robust dual-processor synchronization.