STMicroelectronics HCF4047M013TR

Overview

HCF4047M013TR from STMicroelectronics is a CMOS monostable/astable multivibrator IC with gatable free-running and edge-triggered one-shot operation, buffered Q/Q̅ and OSC outputs, ±100 nA input leakage at 18 V, and operation from 3 V to 20 V supply. It requires only one external R and C for timing and supports retriggerable monostable, external reset, and external counter integration in timing-critical control circuits.

For engineers reviewing the HCF4047M013TR datasheet, HCF4047M013TR pinout, HCF4047M013TR application, or HCF4047M013TR equivalent, key selection criteria include astable period tolerance (±5% typical), monostable pulse width accuracy (±9.3% worst-case), retrigger latency (100–600 ns), and guaranteed symmetrical output drive across 5/10/15 V parametric ratings.

Technical Context

The HCF4047M013TR implements dual-mode multivibrator logic using cascaded flip-flops and gated oscillator stages, enabling simultaneous true/complement buffered outputs with independent ASTABLE and TRIGGER inputs. Its internal architecture supports positive-edge, negative-edge, and retriggerable monostable modes without external logic.

Timing is determined solely by external R–C network connected between pins 1 (C), 2 (R), and 3 (RC-Common); oscillator frequency scales linearly with 1/(RC) in astable mode (t_A = 4.40RC), while monostable pulse width follows t_M = 2.48RC with ±9.3% unit-to-unit variation due to V_TR shift.

Key Specifications

Pinout & Package

Package: SO-14 (Small Outline, 14-pin, surface-mount). Dimensions per STMicroelectronics PO13G: 8.55–8.75 mm length, 5.8–6.2 mm width, 1.27 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar monostable/astable multivibrator applications.

Compared with CD4047BE and MC14541BCP, the HCF4047M013TR uniquely combines adjustable RC timing, retriggerability, true/complement buffered outputs, and 20 V operation-making it the only option supporting precision, low-leakage, and flexible mode switching in modern industrial timing designs.

Availability

HCF4047M013TR is available at Aetrix Electronics and suitable for industrial timer circuits, power supply sequencing, instrumentation signal generation, and legacy system interface timing requiring stable component supply and long-term obsolescence mitigation.

Supply support for HCF4047M013TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for automotive, industrial, and consumer markets.

The HCF4047B series belongs to ST's legacy CMOS logic product line, engineered specifically for robust, low-power timing functions in harsh environments-emphasizing wide supply range, low leakage, and JEDEC-compliant reliability.

FAQ

What is the minimum external capacitor value recommended for stable monostable operation?

STMicroelectronics specifies a minimum external capacitor of 1000 pF for monostable mode to minimize error from stray capacitance and ensure accurate t_M = 2.48RC timing. Values below this threshold increase sensitivity to PCB parasitics and reduce repeatability across units and temperatures.

Can the HCF4047M013TR generate a precise 50% duty cycle square wave?

The Q and Q̅ outputs deliver symmetrical, matched duty cycles with deviation limited to ±0.5% at 5 V and ±0.1% at 15 V. However, the OSC. OUT (Pin 13) is explicitly not guaranteed for 50% duty cycle and should not be used where exact mark-space ratio is required.

How does the retrigger mode affect output pulse termination timing?

In retrigger mode, the Q output remains high until the second positive edge of the internal oscillator appears at Flip-Flop 4 after the final retrigger pulse ends. This introduces a variable delay t_D that depends on oscillator frequency-not on RC values-making it unsuitable for absolute timing but ideal for frequency comparison or pulse extension.

Is external reset required during normal operation, or only at power-up?

External reset (Pin 9) is mandatory at power-on to guarantee a known initial state, especially since the device lacks internal power-on reset. It is also used dynamically to terminate an active monostable or astable output at any time-e.g., for emergency stop or mode switching in safety-critical systems.