Renesas HD64413ASFI

Overview

HD64413ASFI from Renesas Technology Corp. is a SuperH RISC-based peripheral LSI functioning as a dedicated 2D graphics renderer with integrated synchronous DRAM interface, supporting real-time polygon rendering, video capture (YCbCr/RGB), and CRT/TV display output. It operates at 50 MHz CPU clock, integrates Unified Graphics Memory (UGM) management, and targets embedded multimedia systems requiring hardware-accelerated GUI and video overlay.

For engineers reviewing the HD64413ASFI datasheet, HD64413ASFI pinout, HD64413ASFI application, or HD64413ASFI equivalent, key selection considerations include its SDRAM interface timing compliance (×16 64-Mbit), UGM double-buffering control, video input format support (ITU-R BT.601), and register-level command list execution (POLYGON4A, LINEW, JUMP).

Technical Context

The HD64413ASFI implements a fixed-function graphics pipeline tightly coupled to the SH microcomputer architecture, using a command-driven display list engine that fetches and executes drawing instructions from system memory. Its UGM architecture unifies frame buffer, work area, video capture buffer, and palette memory into a single address-mapped region managed via MEMR and DSMR registers.

It supports master-mode CRT timing generation (horizontal sync width up to 128 clocks, vertical scan cycle up to 2048 lines) and TV sync mode with NTSC/PAL-compatible blanking intervals. Video capture operates in 8-bit YCbCr 4:2:2 format with programmable reduction and position offset, feeding directly into UGM for overlay composition.

Key Specifications

Pinout & Package

HD64413ASFI is housed in a 208-pin PQFP (Plastic Quad Flat Package) with 0.5 mm pitch, thermally enhanced for sustained graphics processing. Pin functions are defined across CPU interface, UGM control, display output, video input, and system control domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2D graphics acceleration applications.

Compared with HD64413ASFI, the µPD72865 demands external memory management and adds signal routing overhead, while the HD64412A omits video capture entirely-making HD64413ASFI the sole option among these three supporting integrated BT.601 video ingestion and UGM-based compositing.

Availability

HD64413ASFI is available at Aetrix Electronics and suitable for embedded automotive displays, industrial HMIs, set-top box GUIs, and medical imaging preview systems requiring stable component supply and long-term lifecycle support.

Supply support for HD64413ASFI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Technology Corp. (now part of Renesas Electronics Corporation) is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, and application-specific LSIs for automotive, industrial, and consumer electronics.

The HD64413ASFI belongs to the SuperH Q-Series graphics accelerator family, designed specifically to provide real-time 2D rendering, video capture, and display control for SH-based embedded multimedia systems.

FAQ

What is the primary function of the HD64413ASFI in an embedded system?

The HD64413ASFI serves as a dedicated 2D graphics rendering engine with integrated SDRAM interface and video capture capability. It executes display list commands such as POLYGON4A and LINEW to generate GUI elements, overlays video input (ITU-R BT.601 YCbCr) onto frame buffers, and drives CRT or TV displays with precise timing. In a typical SH-based system, HD64413ASFI offloads graphics tasks from the CPU, enabling deterministic rendering performance.

Does the HD64413ASFI support direct connection to standard SDRAM chips?

Yes, the HD64413ASFI supports direct interface to ×16 64-Mbit SDRAM chips, as confirmed in Section 6.2 of the user's manual. It generates all required SDRAM control signals-including RAS, CAS, WE, and bank select-and auto-configures the SDRAM mode register during initialization. The HD64413ASFI handles refresh cycles internally, eliminating the need for external refresh logic when using compliant SDRAM.

Can the HD64413ASFI render graphics while simultaneously capturing video input?

Yes, the HD64413ASFI supports concurrent rendering and video capture through its Unified Graphics Memory architecture. Video data captured in YCbCr 4:2:2 format is written directly into a designated UGM region, while the display list engine reads from other UGM regions to compose the final output. This parallel operation is enabled by internal arbitration and documented in Sections 3.3 and 6.4 of the HD64413ASFI user's manual.

What video standards does the HD64413ASFI support for input and output?

The HD64413ASFI supports ITU-R BT.601 8-bit YCbCr 4:2:2 for video input, with dedicated VD0–VD7 and VC0–VC7 pins for pixel and sync data. For output, it supports both CRT master mode (programmable H/V timing) and TV sync mode compatible with NTSC and PAL broadcast standards, using HOUT/VOUT signals or external sync locking as described in Section 3.4.4.

Is the HD64413ASFI pin-compatible with earlier Q-Series devices like the HD64412A?

No, the HD64413ASFI is not pin-compatible with the HD64412A. Although both belong to the Q-Series, the HD64413ASFI adds dedicated video input pins (VD0–VD7, VC0–VC7), expanded SDRAM interface signals, and additional interrupt outputs-requiring a distinct 208-pin PQFP layout. Pin configuration differences are explicitly documented in Section 2.1 of the HD64413ASFI user's manual.