Renesas HD6473657HV
- Part No.:
- HD6473657HV
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- -
- Datasheet:
-
HD6473657HV.pdf
- Description:
- 16-BIT, OTPROM, 5MHZ
- Quantity:
- Payment:

- Shipping:

Inventory:133
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
HD6473657HV from Renesas Technology Corp. is a 16-bit single-chip microcontroller in the H8/3657 Series, featuring an H8/300L CPU core, five on-chip timers (including Timer A, B1, V, X, and watchdog), a 14-bit PWM module, dual-channel serial communication interface (SCI), and a 10-bit A/D converter. It operates at up to 20 MHz and targets real-time embedded control applications such as motor drive and industrial automation.
For engineers reviewing the HD6473657HV datasheet, HD6473657HV pinout, HD6473657HV application, or HD6473657HV equivalent, key selection criteria include its 100-pin PQFP package, integrated PWM timing resolution, SCI baud rate flexibility, low-power sleep/standby modes, and compatibility with H8/300L instruction set for legacy code reuse.
Technical Context
The HD6473657HV implements the H8/300L CPU architecture with full instruction set compatibility to the earlier H8/300, supporting 16-bit data paths and 24-bit addressing. Its peripheral integration includes independent clock prescalers for each timer, configurable SCI baud generation via internal BRG, and A/D conversion with software-started or timer-triggered sampling.
Power management is handled through six distinct operating modes-Active, Subactive, Sleep, Standby, Watch, and Subsleep-with oscillator settling times and clock gating explicitly defined per mode. The device supports PROM-mode programming via external socket adapter and features on-chip RAM (2 KB) and ROM (128 KB mask ROM).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | H8/300L 16-bit RISC core, upward-compatible with H8/300 instruction set |
| Max Clock Frequency | 20 MHz system clock; enables deterministic real-time response ≤50 ns instruction cycle |
| Memory | 128 KB on-chip mask ROM + 2 KB on-chip RAM; no external bus required for basic operation |
| PWM Resolution | 14-bit programmable counter; supports precise motor phase control with <1% duty-cycle granularity |
| A/D Converter | 10-bit successive-approximation ADC with 8 input channels; sample-and-hold triggered by software or Timer V |
| Serial Interface | Dual-channel SCI (SCI1 & SCI2); full-duplex UART with programmable baud rate and framing options |
| Timers | Five independent timers: Timer A (input capture/output compare), Timer B1 (8-bit), Timer V (16-bit event counter), Timer X (16-bit reload), and watchdog |
Pinout & Package
HD6473657HV is housed in a 100-pin plastic quad flat pack (PQFP) with 0.65 mm lead pitch, compliant with JEDEC MS-026. Pin functions are multiplexed across I/O ports (Ports 1, 2, 3, 5–9, B) and dedicated peripheral signals including XTAL/EXTAL, RESET, IRQ, and PWM output pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Dual 5 V supply domains: VCC for I/O and core logic, VSS for analog reference and digital ground separation |
| XTAL / EXTAL | Crystal oscillator input/output | Supports 1–20 MHz crystal; drives internal system clock generator and subclock circuitry |
| RESET | Active-low reset input | Asynchronous reset assertion clears CPU registers and initializes peripheral modules to known states |
| IRQ0–IRQ7 | External interrupt request inputs | Level-sensitive or edge-triggered inputs mapped to priority-encoded interrupt vector table |
| TO0–TO3 | PWM output terminals | Four dedicated outputs from Timer A and Timer V; support complementary PWM with dead-time insertion |
| AD0–AD7 | Analog input channels | Eight single-ended inputs shared with Port 5 pins; internally routed to 10-bit A/D converter |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PWM with 14-bit resolution | Enables fine-grained motor speed and torque control without external DAC or timer expansion |
| Dual SCI with independent baud rate generators | Allows simultaneous host communication and fieldbus interface (e.g., Modbus RTU over SCI1 and debug console over SCI2) |
| Five programmable timers with distinct capabilities | Eliminates need for external timing ICs: Timer X for periodic task scheduling, Timer V for encoder pulse counting, watchdog for fail-safe monitoring |
| Six power-down modes with defined wake-up sources | Reduces active current to <10 µA in Standby mode while retaining RAM content and enabling IRQ-based wake-up |
| On-chip 128 KB mask ROM and 2 KB RAM | Supports self-contained firmware execution with no external memory interface, simplifying PCB layout and BOM |
Applications
| Industrial Motor Control | Programmable Logic Controller (PLC) I/O Module |
|---|---|
Use Scenario: Closed-loop control of 3-phase BLDC motors in HVAC blowers and conveyor systems. IC Role / Device Role / Timing Role: Primary controller executing FOC algorithms, generating PWM gate signals, sampling current feedback via A/D, and communicating status over SCI. Use Value: Integrated 14-bit PWM and 10-bit ADC enable <±0.5% speed regulation accuracy without external signal conditioning. |
Use Scenario: Digital input/output expansion module with isolated field-side interfaces and backplane communication. IC Role / Device Role / Timing Role: Local intelligence unit managing opto-isolated DI/DO state scanning, debounce timing, and Modbus RTU packet assembly. Use Value: Five independent timers allow concurrent scan cycles (e.g., 10 ms DI polling, 100 ms DO update, 1 s diagnostics) without CPU overhead. |
| Factory Automation Sensor Node | Energy Metering Front-End Controller |
Use Scenario: Wireless sensor node aggregating temperature, pressure, and vibration data for predictive maintenance. IC Role / Device Role / Timing Role: Data acquisition hub triggering A/D conversions on Timer V overflow, buffering samples in on-chip RAM, and formatting packets for RF transmission. Use Value: Subsleep mode draws <20 µA while maintaining timer accuracy for scheduled wake-ups, extending battery life to >5 years. |
Use Scenario: Residential electricity meter with pulse counting, tariff switching, and LCD display control. IC Role / Device Role / Timing Role: System-on-chip managing metrology IC interface (via SCI), real-time clock synchronization, tamper detection, and segmented LCD driver timing. Use Value: Dual SCI channels permit simultaneous connection to metrology ASIC and IR/RF communication interface without UART bridging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HD64F3657FV | Same H8/3657 architecture but uses flash memory (not mask ROM); supports in-system reprogramming. | Preferred where firmware updates are required post-deployment; lacks HD6473657HV's production-optimized mask ROM density. | Select HD64F3657FV when field upgradeability outweighs cost and security advantages of mask ROM. |
| R5F3657EDFP | Successor device in Renesas' RX600 series; 32-bit CPU, higher clock (100 MHz), enhanced peripherals (CAN, USB), larger memory. | Targets next-generation designs requiring CAN bus, floating-point math, or multi-threaded RTOS support. | Choose R5F3657EDFP only if new design mandates 32-bit performance or automotive-grade interfaces; not drop-in compatible. |
Compared with HD6473657HV, HD64F3657FV trades mask-ROM permanence for flash flexibility, while R5F3657EDFP replaces the entire 16-bit H8 platform with a 32-bit architecture-making HD6473657HV optimal for cost-sensitive, high-volume, fixed-function control where legacy code stability and minimal BOM count are critical.
Availability
HD6473657HV is available at Aetrix Electronics and suitable for industrial motor control, PLC I/O modules, factory sensor nodes, and energy metering front-ends requiring stable component supply and long-term production continuity.
Supply support for HD6473657HV includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Technology Corp. was formed in 2003 through the merger of Hitachi and Mitsubishi Electric's semiconductor operations, specializing in microcontrollers, analog, and power devices for industrial and embedded markets.
The H8/3657 Series-including HD6473657HV-was designed for cost-effective, real-time control in resource-constrained systems where deterministic timing, low power, and peripheral integration outweigh raw processing throughput.
FAQ
What is the maximum operating frequency of the HD6473657HV?
The HD6473657HV supports a maximum system clock frequency of 20 MHz, achieved using an external crystal (1–20 MHz) connected to the XTAL/EXTAL pins. At this frequency, the CPU executes instructions in 50 ns cycles, enabling tight real-time loop timing for motor control and sensor sampling tasks. The HD6473657HV datasheet specifies timing margins for all peripheral modules-including A/D conversion and SCI baud generation-at this maximum clock rate.
Does the HD6473657HV include on-chip flash memory?
No, the HD6473657HV contains 128 KB of mask-programmed ROM, not flash memory. This makes it suitable for high-volume, fixed-firmware applications where code immutability, cost reduction, and resistance to accidental overwrite are priorities. For flash-based alternatives, consider the HD64F3657FV, which shares the same pinout and peripheral set but replaces mask ROM with reprogrammable flash. The HD6473657HV itself requires external programming during wafer fabrication.
How many analog input channels does the HD6473657HV support?
The HD6473657HV integrates a 10-bit successive-approximation A/D converter with eight analog input channels (AD0–AD7), multiplexed onto Port 5 pins. These channels support both single-ended and pseudo-differential configurations, with conversion triggered by software command or Timer V overflow. The HD6473657HV's A/D module includes built-in sample-and-hold and reference voltage options (AVCC or internal bandgap), enabling accurate sensor signal digitization without external components.
What power-saving modes are available on the HD6473657HV?
The HD6473657HV offers six configurable power-down modes: Sleep, Standby, Watch, Subsleep, Subactive, and Active (Medium-Speed). In Standby mode, current drops below 10 µA while preserving RAM contents and allowing wake-up via IRQ or reset. Subsleep mode maintains timer accuracy for periodic wake-ups at ~20 µA. Each mode has documented oscillator settling times and peripheral disable rules-critical for designing battery-powered nodes where the HD6473657HV serves as the sole system controller.
Is the HD6473657HV pin-compatible with other H8/3657 Series devices?
Yes, the HD6473657HV shares the same 100-pin PQFP package and pin assignment with other members of the H8/3657 family, including HD64F3657FV and HD6433657. This allows hardware design reuse across mask-ROM and flash variants. However, differences in memory type (mask ROM vs. flash), reset behavior, and boot configuration mean firmware and initialization sequences may require adjustment-even though the HD6473657HV pinout remains identical across the series.
HD6473657HV Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- -
- Series:
- *
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- -
- Core Size:
- -
- Speed:
- -
- Connectivity:
- -
- Peripherals:
- -
- Number of I/O:
- -
- Program Memory Size:
- -
- Program Memory Type:
- -
- EEPROM Size:
- -
- RAM Size:
- -
- Voltage - Supply (Vcc/Vdd):
- -
- Data Converters:
- -
- Oscillator Type:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
HD6473657HV FAQ
1.How can I place an order for HD6473657HV through Aetrix?
Please submit a Request for Quotation (RFQ) for HD6473657HV on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HD6473657HV reliable?
The price and inventory of HD6473657HV are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HD6473657HV is usually 5 days.
3.What payment methods are accepted for HD6473657HV?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HD6473657HV transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HD6473657HV?
HD6473657HV orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HD6473657HV order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HD6473657HV?
For technical support, including HD6473657HV datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HD6473657HV requirements.
6.How does Aetrix verify that HD6473657HV is sourced from the original manufacturer or authorized distributors?
All HD6473657HV products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HD6473657HV meets industry standards.
7.What is the process for return or replacement of HD6473657HV?
All HD6473657HV units undergo pre-shipment inspection (PSI). If there is an issue with HD6473657HV, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HD6473657HV part is unused and in its original packaging.
Return procedure for HD6473657HV:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
HD6473657HV Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

