My Inquiry
My Account
NXP Semiconductors HEF4000BT,652
- Part No.:
- HEF4000BT,652
- Manufacturer:
- NXP Semiconductors
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
HEF4000BT,652.pdf
- Description:
- IC DUAL 3-IN NOR GATE 14-SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:4,403
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
HEF4000BT,652 from NXP Semiconductors (formerly Philips) is a dual 3-input NOR gate and single inverter IC in the HEF4000B LOCMOS logic family. It operates across 3 V to 15 V supply, delivers buffered outputs with high noise immunity, and supports propagation delays as low as 12 ns at 15 V with 50 pF load - used in digital control logic, reset sequencing, and combinational logic blocks in industrial timers and power management systems.
For engineers reviewing the HEF4000BT,652 datasheet, HEF4000BT,652 pinout, HEF4000BT,652 application, or HEF4000BT,652 equivalent, key selection factors include its dual-NOR + inverter integration in SO14 package, unbuffered inverter stage usable as analog amplifier, VDD range (3–15 V), output drive capability, and LOCMOS-compatible input thresholds.
Technical Context
The HEF4000BT,652 implements two independent 3-input NOR gates (I1–I3→O1; I4–I6→O2) and one unbuffered inverter stage (I7→O3). Its fully buffered NOR outputs ensure stable switching and pattern-insensitive impedance, while the unbuffered inverter enables linear-mode operation for analog gain applications.
It belongs to the HE4000B LOCMOS family, characterized by low power consumption, CMOS-level input compatibility, and rail-to-rail output swing. DC input voltage thresholds follow standard HE4000B specifications, and AC performance is specified at Tamb = 25 °C with CL = 50 pF and input transition ≤20 ns.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 3 V to 15 V - supports wide-range industrial and battery-powered systems without level-shifting. |
| Propagation Delay (I7→O3, 15 V) | 20 ns max - enables use as fast digital inverter or analog amplifier with predictable timing. |
| Propagation Delay (I1→O1, 15 V) | 55 ns max - defines worst-case combinatorial path delay in NOR-based logic trees. |
| Output Drive (VOH/VOL) | Rail-to-rail swing - ensures full logic swing into standard CMOS/TTL loads without external pull-ups. |
| Input Thresholds | VIL ≤ 0.3×VDD, VIH ≥ 0.7×VDD - compatible with standard CMOS logic families and microcontroller GPIOs. |
| Dynamic Power (10 V, fi=1 MHz) | ~7.7 mW typical - enables low-power logic implementation in always-on control subsystems. |
Pinout & Package
HEF4000BT,652 is housed in a 14-lead small outline (SO) plastic package (SOT108-1), pin-compatible with industry-standard SO14 footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | NOR Gate 1 Input A (I1) | First input of first 3-input NOR gate; CMOS-compatible threshold. |
| 2 | NOR Gate 1 Input B (I2) | Second input of first 3-input NOR gate; no internal pull-up/down. |
| 3 | NOR Gate 1 Input C (I3) | Third input of first 3-input NOR gate; all three must be LOW for HIGH output. |
| 4 | NOR Gate 1 Output (O1) | Buffered active-low output; drives up to 10 LSTTL loads. |
| 5 | NOR Gate 2 Input A (I4) | First input of second 3-input NOR gate; electrically identical to I1. |
| 6 | NOR Gate 2 Input B (I5) | Second input of second 3-input NOR gate; shares same DC/AC specs as I2. |
| 7 | GND | Ground reference for all logic and power domains; requires low-impedance PCB connection. |
| 8 | VDD | Positive supply rail (3–15 V); decoupling capacitor recommended near pin. |
| 9 | NOR Gate 2 Input C (I6) | Third input of second 3-input NOR gate; completes 3-input logic function. |
| 10 | NOR Gate 2 Output (O2) | Buffered active-low output; independent of O1; fan-out matched to O1. |
| 11 | Inverter Input (I7) | Input to unbuffered inverter stage; usable for analog amplification when biased. |
| 12 | Inverter Output (O3) | Unbuffered output; exhibits higher gain and lower drive strength than O1/O2. |
| 13 | No Connect | Internally unused; must remain floating or tied to GND per design guidelines. |
| 14 | No Connect | Internally unused; must remain floating or tied to GND per design guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 3-input NOR + single inverter | Reduces board space vs discrete gate arrays; enables compact reset or enable logic with minimal external components. |
| Fully buffered NOR outputs | Ensures consistent edge rates and noise rejection across varying load conditions and signal patterns. |
| Unbuffered inverter stage (I7/O3) | Supports linear-mode biasing for analog functions like oscillator core or low-gain amplifier without external transistors. |
| LOCMOS technology | Delivers CMOS-level power efficiency with TTL-compatible drive strength and robust ESD tolerance (±2 kV HBM). |
| Wide VDD range (3–15 V) | Eliminates need for separate voltage regulators in mixed-supply systems such as PLC I/O modules or motor controllers. |
Applications
| Industrial Timer Logic | Power Sequencing Control |
|---|---|
Use Scenario: Generating precise time-delayed reset pulses in programmable logic controllers and relay timers. IC Role / Device Role / Timing Role: Dual NOR gates implement cross-coupled latch and delay-chain logic; unbuffered inverter provides RC-timed feedback. Use Value: Eliminates external monostable ICs and reduces component count while maintaining timing accuracy over temperature. | Use Scenario: Enabling multi-rail power supplies in embedded systems where 3.3 V, 5 V, and 12 V rails must power up in strict sequence. IC Role / Device Role / Timing Role: NOR gates act as AND-NOT combinational logic for enable/disable interlocks; inverter buffers supervisor signals. Use Value: Ensures safe power-up order without FPGA or microcontroller intervention, reducing firmware complexity. |
| Analog Signal Conditioning | Digital Interface Level Translation |
Use Scenario: Building low-frequency oscillator or gain stage in sensor front-ends where cost and board area are critical. IC Role / Device Role / Timing Role: Unbuffered inverter (I7/O3) biased in linear region serves as single-transistor-equivalent amplifier. Use Value: Achieves ~10–20 dB gain at sub-MHz frequencies using only passive biasing - no additional active devices required. | Use Scenario: Interfacing legacy 5 V logic peripherals with modern 3.3 V microcontrollers in industrial HMI panels. IC Role / Device Role / Timing Role: NOR gates configured as inverters provide level-shifted, noise-immune signal inversion between voltage domains. Use Value: Maintains signal integrity and timing margins without dedicated level translators or resistor networks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4000BE | Standard CD4000-series CMOS; higher propagation delay (150 ns @ 5 V), no unbuffered inverter stage. | Limited to digital-only use; cannot replace HEF4000BT,652 in analog amplifier configurations. | Select when only basic NOR/inverter logic is needed and wider VDD tolerance (3–18 V) is prioritized over speed or analog functionality. |
| 74HC02D | High-speed CMOS; dual 2-input NOR only; no inverter; SO14 package; VDD = 2–6 V only. | Cannot implement 3-input NOR or analog functions; incompatible with >6 V systems. | Choose for faster switching (<20 ns @ 5 V) in 3.3/5 V digital-only designs where 3-input logic is implemented externally. |
Compared with CD4000BE and 74HC02D, the HEF4000BT,652 uniquely combines dual 3-input NOR, an unbuffered inverter for analog use, and 3–15 V operation - making it irreplaceable in mixed-signal timing and power-control applications requiring both logic density and analog flexibility.
Availability
HEF4000BT,652 is available at Aetrix Electronics and suitable for industrial timer logic, power sequencing control, analog signal conditioning, and digital interface level translation requiring stable component supply and long-term obsolescence resilience.
Supply support for HEF4000BT,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications.
The HEF4000BT,652 belongs to the legacy HE4000B LOCMOS logic family, designed for robust, low-power digital control in harsh environments - especially where wide supply range, noise immunity, and analog-digital coexistence are essential.
FAQ
What is the maximum operating supply voltage for the HEF4000BT,652?
The HEF4000BT,652 supports a maximum supply voltage of 15 V, with guaranteed operation across 3 V to 15 V. This wide VDD range allows direct integration into systems with mixed-voltage rails - such as industrial controllers using both 5 V and 12 V supplies - without external regulation. Operation beyond 15 V risks permanent damage and is not supported per the January 1995 Philips datasheet.
Can the HEF4000BT,652 be used as an analog amplifier?
Yes - the unbuffered inverter stage (I7/O3) in the HEF4000BT,652 can be biased into its linear region to function as a low-gain analog amplifier or oscillator core. Figures 4–8 in the original Philips datasheet confirm voltage gain, transconductance, and bias behavior. This capability is unique to the HEF4000BT,652 among dual-NOR logic ICs and is not available in buffered-only alternatives like 74HC02D.
Is the HEF4000BT,652 pin-compatible with other HEF4000B variants?
Yes - the HEF4000BT,652 uses the SOT108-1 (SO14) package and shares identical pinout with HEF4000BP (DIP) and HEF4000BD (CERDIP) variants. All HEF4000B part numbers implement the same logic function and terminal mapping; only package type and thermal/mechanical properties differ. No PCB redesign is needed when migrating from DIP to SO package versions.
What is the purpose of pins 13 and 14 on the HEF4000BT,652?
Pins 13 and 14 on the HEF4000BT,652 are internally unconnected (No Connect). Per the Philips datasheet, they must remain floating or be tied to GND - never driven or connected to VDD. Leaving them unconnected avoids parasitic coupling; grounding them improves noise margin in high-EMI environments. These pins do not affect logic operation or timing of the HEF4000BT,652.
How does the HEF4000BT,652 compare to standard 74-series logic in terms of noise immunity?
The HEF4000BT,652 offers superior noise immunity compared to bipolar 74-series logic due to its fully buffered outputs and LOCMOS input structure - resulting in higher input impedance, lower input current, and greater hysteresis margin. Its output impedance remains stable across signal patterns, unlike unbuffered gates. This makes the HEF4000BT,652 especially reliable in electrically noisy industrial settings where 74LS02 or 74F02 may exhibit metastability or false triggering.
HEF4000BT,652 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 4000B
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- NOR/INVERT Gate
- Number of Circuits:
- 2
- Number of Inputs:
- 7 Input (3, 3, 1)
- Schmitt Trigger Input:
- No
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 3mA, 3mA
- Voltage - Supply:
- 3V ~ 15V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
HEF4000BT,652 FAQ
1.How can I place an order for HEF4000BT,652 through Aetrix?
Please submit a Request for Quotation (RFQ) for HEF4000BT,652 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HEF4000BT,652 reliable?
The price and inventory of HEF4000BT,652 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HEF4000BT,652 is usually 5 days.
3.What payment methods are accepted for HEF4000BT,652?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HEF4000BT,652 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HEF4000BT,652?
HEF4000BT,652 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HEF4000BT,652 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HEF4000BT,652?
For technical support, including HEF4000BT,652 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HEF4000BT,652 requirements.
6.How does Aetrix verify that HEF4000BT,652 is sourced from the original manufacturer or authorized distributors?
All HEF4000BT,652 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HEF4000BT,652 meets industry standards.
7.What is the process for return or replacement of HEF4000BT,652?
All HEF4000BT,652 units undergo pre-shipment inspection (PSI). If there is an issue with HEF4000BT,652, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HEF4000BT,652 part is unused and in its original packaging.
Return procedure for HEF4000BT,652:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
HEF4000BT,652 Tags
-
SN74LVC1G97DCKR
Texas Instruments
-
SN74LVC1G97DRLR
Texas Instruments
-
SN74LVC1G97DBVR
Texas Instruments
-
NC7SZ57P6X
onsemi
-
SN74LVC1G97DCKT
Texas Instruments
-
MC100EP05DTR2G
onsemi
-
MC100EP08DTR2G
onsemi
-
NB7L86AMNHTBG
onsemi
-
HMC722LP3E
Analog Devices Inc.
-
74LVC1G97GW,125
Nexperia USA Inc.
-
74LVC1G57GW,125
Nexperia USA Inc.
-
74LVC1G97GV,125
Nexperia USA Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
