Nexperia USA Inc. HEF4007UBT,652

Overview

HEF4007UBT,652 from Nexperia is a dual complementary pair and inverter IC containing three matched CMOS transistor pairs (two n-channel/p-channel pairs plus one shared drain complementary pair) in a single SO14 package. It operates from 3.0 V to 15.0 V, delivers ±3.6 mA output drive at 15 V, supports -40 °C to +85 °C ambient operation, and features integrated input clamp diodes enabling overvoltage-tolerant interfacing - used in crystal oscillators, high-impedance buffers, and analog amplifier stages.

For engineers reviewing the HEF4007UBT,652 datasheet, HEF4007UBT,652 pinout, HEF4007UBT,652 application, or HEF4007UBT,652 equivalent, key selection criteria include supply voltage range (3–15 V), output current capability (±3.6 mA @15 V), propagation delay (15–80 ns depending on VDD and load), thermal operating range (-40 to +85 °C), and SO14 package compatibility with standard PCB footprints.

Technical Context

The HEF4007UBT,652 implements three independent complementary transistor pairs: two full n/p pairs (DP1/DN1/G1 and DP2/DN2/G2) and a third pair sharing a common drain (DN/P3) with dedicated source terminals (SP3/SN3) and gate (G3). Its functional diagram confirms discrete-level transistor-level control - not logic-gate behavior - enabling analog biasing, linear amplification, and oscillator feedback paths.

Input clamp diodes referenced to VDD and VSS allow safe interface with signals exceeding supply rails when used with current-limiting resistors. The device requires strict adherence to substrate isolation rules: VDD (Pin 14) and VSS (Pin 7) must remain the most positive potentials relative to all other pins to prevent latch-up or permanent damage.

Key Specifications

Pinout & Package

HEF4007UBT,652 is housed in a plastic small outline package (SO14) per SOT108-1 standard: 14-pin, 3.9 mm body width, 1.27 mm lead pitch, and gull-wing surface-mount leads compatible with IPC-7351B footprint requirements.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar complementary transistor pair applications.

Compared with CD4007UBM96 and MC14007UBDR2G, the HEF4007UBT,652 offers superior output drive (±3.6 mA) and faster propagation (15 ns min @15 V), making it optimal for high-frequency oscillator and high-current driver roles - while both alternatives trade drive strength or speed for extended temperature or logic-compatibility advantages.

Availability

HEF4007UBT,652 is available at Aetrix Electronics and suitable for crystal oscillator modules, industrial sensor interface boards, and high-impedance analog signal conditioning circuits requiring stable component supply across long production lifecycles.

Supply support for HEF4007UBT,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions optimized for efficiency, miniaturization, and robustness in industrial, automotive, and consumer applications.

The HEF4007UBT,652 belongs to Nexperia's legacy CMOS logic family designed specifically for analog-friendly digital building blocks - enabling oscillator, amplifier, and driver functions in space-constrained mixed-signal systems without discrete transistor arrays.

FAQ

What is the maximum safe supply voltage for HEF4007UBT,652?

The absolute maximum supply voltage is +18 V (per Table 3), but recommended operation is limited to 3.0 V to 15.0 V (Table 4). Exceeding 15.0 V risks accelerated aging, increased leakage, and reduced long-term reliability - even if within absolute maximum ratings. Operation above 15.0 V voids specification guarantees for VOH, VOL, and propagation delay.

Can HEF4007UBT,652 be used as a linear amplifier?

Yes - its matched n/p transistor pairs support linear amplifier configurations. Figure 7 shows a verified test setup achieving 25× voltage gain at 15 V supply. Key design requirements include proper DC biasing via external resistors, maintaining VDD/VSS as most-positive potentials, and limiting input swing to avoid cutoff/saturation regions where gm drops significantly.

Why must VDD and VSS be the most positive potentials relative to all other pins?

This requirement prevents forward-biasing parasitic substrate diodes between transistor wells and the monolithic silicon substrate. Violation causes unintended current paths, latch-up, thermal runaway, or permanent junction damage. It is a fundamental layout constraint - not an optional recommendation - enforced by the device's internal CMOS process architecture.

Does HEF4007UBT,652 support 3.3 V logic-level inputs?

Yes - VIH is specified as ≥12.5 V at 15 V supply, ≥8 V at 10 V, and ≥4 V at 5 V (Table 5), meaning 3.3 V inputs fall below guaranteed HIGH recognition at all supply levels. However, actual switching thresholds are near 0.5 × VDD (Fig. 4), so 3.3 V inputs reliably trigger at VDD ≥ 6.6 V. For 3.3 V-only systems, level translation is required.