NXP Semiconductors HEF40098BP,652

Overview

HEF40098BP,652 from Nexperia is a hex inverting buffer IC with dual 3-state enable control (1OE and 2OE), delivering six active-low outputs across two independent groups (1Y0–1Y3 and 2Y0–2Y1), operating from 3 V to 15 V supply, and rated for −40 °C to +85 °C ambient - used in bus interface isolation and level-shifting logic systems.

For engineers reviewing the HEF40098BP,652 datasheet, HEF40098BP,652 pinout, HEF40098BP,652 application, or HEF40098BP,652 equivalent, key selection concerns include 3-state timing asymmetry (tPHZ/tPLZ vs tPZH/tPZL), voltage-scalable propagation delay (22–80 ns at VDD = 15 V/5 V), output drive capability (up to 24 mA sink at 15 V), and SO16 package compatibility with legacy 4000-series PCB footprints.

Technical Context

The HEF40098BP,652 implements static CMOS logic with fully symmetrical output drive characteristics and JEDEC JESD13-B compliance. Its architecture separates six inverters into two independently enabled groups: four buffered outputs (1Y0–1Y3) respond to 1OE, while two (2Y0–2Y1) respond to 2OE - both enables are active LOW.

It supports wide-supply operation (3–15 V) with input thresholds scaling proportionally (e.g., VIH = 11.0 V at VDD = 15 V), and features low static current (≤120 µA at 15 V, 85 °C) and high-impedance OFF-state leakage ≤12.0 µA. Dynamic performance is load-dependent, with propagation delays defined by extrapolation formulas incorporating CL.

Key Specifications

Pinout & Package

HEF40098BP,652 is housed in a plastic small outline package (SO16), SOT109-1 variant, with 16 leads and 3.9 mm body width - compatible with standard SOIC-16 footprint and reflow profiles.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar hex inverting buffer with 3-state applications.

Compared with CD4009UBE and 74HC05PW,118, the HEF40098BP,652 uniquely delivers dual independent 3-state control in a wide-supply CMOS package - enabling selective bus segmentation and direct 15 V interface without level translation, at the cost of slightly higher propagation latency than HC-series parts.

Availability

HEF40098BP,652 is available at Aetrix Electronics and suitable for industrial bus interface, legacy system level-shifting, test equipment signal gating, and programmable logic I/O expansion requiring stable component supply and long-term obsolescence management.

Supply support for HEF40098BP,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor manufacturer specializing in high-performance logic, analog, and discrete components, with global manufacturing and logistics infrastructure.

The HEF40098BP,652 belongs to Nexperia's legacy-compatible 4000B series - designed for industrial and automotive-adjacent applications requiring wide-supply tolerance, robust ESD immunity, and long-lifecycle support.

FAQ

What is the maximum supply voltage rating for HEF40098BP,652?

The HEF40098BP,652 has an absolute maximum supply voltage (VDD) of +18 V, but its recommended operating range is 3 V to 15 V. Operation above 15 V voids guaranteed parametric performance and risks permanent damage per IEC 60134 limiting values - always observe the 15 V upper limit in functional designs.

How does the dual enable architecture of HEF40098BP,652 improve bus system design?

The HEF40098BP,652 uses two independent active-LOW enables (1OE and 2OE) to separately control four and two outputs, allowing partial bus isolation - for example, holding a 4-bit control bus active while releasing a 2-bit status bus. This eliminates need for extra logic or multiplexers in segmented interface topologies.

Can HEF40098BP,652 drive a 50 pF load at 15 V with guaranteed timing?

Yes - the HEF40098BP,652 dynamic characteristics specify tPHL/tPLH with CL = 50 pF (e.g., 25 ns typical @ 15 V). The extrapolation formula tPHL = 22 ns + (0.06 ns/pF) × CL yields 25 ns at 50 pF, matching the datasheet's typical value and confirming reliable timing under that load condition.

Is HEF40098BP,652 pin-compatible with older HEF40098B variants?

Yes - HEF40098BP,652 uses the SO16 package (SOT109-1) with identical pinout to HEF40098BT and prior revisions. Pin assignments, electrical behavior, and thermal specs are fully aligned per Rev. 9 datasheet, enabling drop-in replacement in existing SOIC-16 layouts.

What is the OFF-state output leakage current specification for HEF40098BP,652?

The HEF40098BP,652 specifies IOZ (OFF-state output current) up to 12.0 µA maximum at VDD = 15 V and Tamb = 85 °C. This low leakage ensures minimal bus loading during high-impedance mode - critical for maintaining signal integrity on shared lines with multiple 3-state devices.