NXP Semiconductors HEF4013BP,652
- Part No.:
- HEF4013BP,652
- Manufacturer:
- NXP Semiconductors
- Category:
- Flip Flops
- Package:
- 14-DIP (0.300", 7.62mm)
- Datasheet:
-
HEF4013BP,652.pdf
- Description:
- IC FF D-TYPE DUAL 1BIT 14DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
HEF4013BP,652 from Nexperia is a dual D-type flip-flop with independent asynchronous set and clear inputs, positive-edge-triggered clock, and Schmitt-trigger clock input for tolerance to slow signal edges. It operates across 3.0 V to 15.0 V supply, supports -40 °C to +125 °C ambient range, and delivers symmetrical CMOS output drive in a 14-lead SO package. It is used in binary counters, shift registers, and toggle configurations requiring deterministic edge-triggered storage.
For engineers reviewing the HEF4013BP,652 datasheet, HEF4013BP,652 pinout, HEF4013BP,652 application, or HEF4013BP,652 equivalent, key selection considerations include its dual independent flip-flop architecture, 15 V absolute maximum supply rating, Schmitt-trigger clock input enabling robust timing in noisy environments, guaranteed operation at 125 °C, and compatibility with legacy 4000-series logic voltage scaling.
Technical Context
The HEF4013BP,652 implements two identical, electrically isolated D-type flip-flops sharing no internal logic-each with dedicated data (D), clock (CP), set-direct (SD), clear-direct (CD), true (Q), and complement (Q̅) terminals. Its Schmitt-trigger clock input provides hysteresis (typical 1.5 V at VDD = 5 V), eliminating need for external signal conditioning on slow-rising clocks.
Each flip-flop responds only to LOW-to-HIGH transitions on its CP input, while SD and CD are active-HIGH asynchronous controls overriding clock and data states. The device uses standard CMOS silicon process, delivering static operation with zero DC current draw in steady state and input leakage below ±1.0 μA at 125 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 3.0 V to 15.0 V - Enables direct interface with legacy 5 V, industrial 10 V, and high-voltage 15 V logic systems without level-shifting. |
| Operating Temperature | -40 °C to +125 °C - Qualified for under-hood automotive, industrial control, and extended-temperature embedded applications. |
| Propagation Delay (tPHL/tPLH) | 30 ns max at VDD = 15 V, CL = 50 pF - Supports reliable 20 MHz clock operation in synchronous counter/divider designs. |
| Input Hysteresis (Schmitt) | Typical 1.5 V at VDD = 5 V - Allows clean clock edge detection on RC-filtered or long-trace signals without oscillation. |
| Output Drive Strength | IOL = 4.2 mA / IOH = -4.2 mA at VDD = 15 V - Sufficient to directly drive multiple 4000-series inputs or small LED loads. |
| ESD Rating | HBM > 2000 V, CDM > 1000 V - Meets JEDEC JS-001/JS-002 Class 2/C3 for robust handling in manual assembly and field service. |
| Static Power Dissipation | IDDS = 120 μA max at VDD = 15 V, Tamb = 125 °C - Enables ultra-low-power latching in battery-backed or energy-constrained systems. |
Pinout & Package
HEF4013BP,652 is supplied in a plastic small outline package (SO14) per SOT108-1, with 3.9 mm body width, 1.27 mm lead pitch, and gull-wing leads suitable for reflow soldering. Pin 1 is marked by a bevelled corner or notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 13 | 1Q, 2Q | True outputs - Active HIGH logic levels referenced to VDD; each drives one flip-flop's Q state independently. |
| 2, 12 | 1Q̅, 2Q̅ | Complement outputs - Inverted logic of corresponding Q outputs; enables direct implementation of toggle or T-type behavior. |
| 3, 11 | 1CP, 2CP | Clock inputs - Positive-edge triggered; Schmitt-triggered for noise immunity on slow-rising waveforms. |
| 4, 10 | 1CD, 2CD | Asynchronous clear - Active HIGH; forces Q = LOW and Q̅ = HIGH regardless of clock or data state. |
| 5, 9 | 1D, 2D | Data inputs - Sampled on rising clock edge; hold time requirement of 15 ns at 15 V ensures setup/hold margin in mixed-slew systems. |
| 6, 8 | 1SD, 2SD | Asynchronous set - Active HIGH; forces Q = HIGH and Q̅ = LOW independent of clock or data. |
| 7 | VSS | Ground reference - 0 V return path for all internal circuitry and output loads; must be low-impedance. |
| 14 | VDD | Supply voltage - Accepts 3–15 V; decoupling capacitor (100 nF) required within 10 mm of this pin for stable switching. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent flip-flops | Two fully isolated storage elements enable simultaneous but separate data capture-no shared control or timing constraints between FF1 and FF2. |
| Schmitt-trigger clock input | Eliminates need for external RC filtering or comparators when interfacing with microcontroller GPIOs, mechanical switch debouncing, or slow oscillator sources. |
| Wide voltage operation (3–15 V) | Supports direct integration into multi-rail systems-e.g., 5 V MCU control logic driving 12 V analog subsystems via level-tolerant I/O. |
| Asynchronous set/clear per flip-flop | Enables immediate initialization or forced reset without waiting for next clock edge-critical for power-on sequencing and fault recovery. |
| High-temperature qualification | Guaranteed functionality at +125 °C ambient allows use in engine control units, motor drives, and enclosed industrial enclosures without derating. |
Applications
| Binary Ripple Counter | Toggle Flip-Flop |
|---|---|
Use Scenario: Cascading multiple HEF4013BP,652 devices to construct a 4-bit or 8-bit asynchronous counter for frequency division or event counting in PLC timer modules. IC Role / Device Role / Timing Role: Each HEF4013BP,652 provides two divide-by-2 stages; Q̅ output of one stage feeds CP of the next, forming a ripple chain with cumulative propagation delay. Use Value: Delivers precise integer division ratios (e.g., ÷2, ÷4, ÷8) using only passive interconnect-no firmware or clock management required. | Use Scenario: Configuring a single HEF4013BP,652 flip-flop as a toggle element by connecting Q̅ to D, enabling clock division by two in digital clock distribution networks. IC Role / Device Role / Timing Role: HEF4013BP,652 functions as a self-triggered T-type flip-flop; each rising clock edge toggles Q state, producing a 50% duty-cycle square wave at half input frequency. Use Value: Provides hardware-based clock halving with sub-30 ns jitter accumulation-superior to software-based division in real-time timing-critical paths. |
| Shift Register Stage | Register Initialization Circuit |
Use Scenario: Using one HEF4013BP,652 as two bits of a serial-in, parallel-out shift register in LED display drivers or sensor data acquisition interfaces. IC Role / Device Role / Timing Role: HEF4013BP,652 stores sequential bit values shifted in via D inputs synchronized to a common CP; Q outputs provide parallel readout. Use Value: Enables compact, low-pin-count serial-to-parallel conversion without microcontroller GPIO overhead or external memory. | Use Scenario: Employing both asynchronous SD and CD inputs of HEF4013BP,652 to force known logic states during system power-up or fault recovery in safety-critical control logic. IC Role / Device Role / Timing Role: HEF4013BP,652 acts as a deterministic latch initializer-SD and CD pins driven by POR (power-on reset) or watchdog signals to guarantee defined Q/Q̅ states before clock activation. Use Value: Prevents metastability or undefined startup behavior in sequenced logic blocks, meeting IEC 61508 functional safety requirements for deterministic initialization. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4013BE | Same pinout and function; wider propagation delay (120 ns max at 5 V), lower ESD rating (HBM ~2 kV), and narrower temp range (-55 °C to +125 °C). | Less suitable for high-speed 15 V systems or harsh industrial environments requiring full 125 °C operation with robust ESD. | Select CD4013BE only for cost-sensitive, non-automotive 5 V designs where speed and ESD margins are secondary. |
| 74HC74D | Higher speed (19 ns typ at 4.5 V), lower VDD range (2–6 V), no Schmitt-trigger clock, and different pinout (non-pin-compatible). | Not usable as drop-in replacement; requires PCB redesign and logic-level adaptation for 5 V TTL/CMOS systems needing faster timing. | Choose 74HC74D for new 5 V high-speed designs where Schmitt triggering is unnecessary and layout flexibility exists. |
Compared with CD4013BE and 74HC74D, the HEF4013BP,652 uniquely balances wide voltage scalability (3–15 V), integrated Schmitt-trigger clock resilience, and full industrial temperature compliance-making it optimal for legacy-compatible, noise-prone, or multi-voltage embedded control applications.
Availability
HEF4013BP,652 is available at Aetrix Electronics and suitable for binary counters, shift registers, and toggle flip-flop circuits requiring stable component supply across automotive under-hood, industrial automation, and aerospace avionics programs.
Supply support for HEF4013BP,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.
The HEF4013BP,652 belongs to Nexperia's legacy-compatible 4000B-series logic family, designed specifically to replace aging HEF4013B variants while maintaining full electrical and mechanical backward compatibility in high-reliability, extended-temperature applications.
FAQ
What is the maximum clock frequency supported by the HEF4013BP,652?
The HEF4013BP,652 supports up to 40 MHz maximum clock frequency at VDD = 15 V and Tamb = 25 °C, as specified in Table 7 of the datasheet. At 125 °C, the practical limit reduces due to increased propagation delay; design margin should include derating to ~25 MHz for full-temperature operation. The HEF4013BP,652 achieves this using optimized CMOS gate sizing and Schmitt-trigger input buffering to maintain edge integrity.
Does the HEF4013BP,652 require external pull-up or pull-down resistors on its inputs?
No, the HEF4013BP,652 does not require external pull-up or pull-down resistors on its inputs. Its CMOS inputs have negligible leakage (<±1.0 μA at 125 °C), and the Schmitt-trigger clock input provides built-in hysteresis. Unused inputs should be tied to VDD or VSS to prevent floating states-direct connection suffices without resistors. This simplifies board layout and reduces BOM count for the HEF4013BP,652.
Can the HEF4013BP,652 operate reliably at 15 V supply with full functionality?
Yes, the HEF4013BP,652 is fully characterized and guaranteed to operate at 15 V supply across its entire -40 °C to +125 °C temperature range. Static and dynamic parameters-including VOH, VOL, propagation delay, and power dissipation-are explicitly rated at 15 V in Tables 5, 6, and 7. The HEF4013BP,652's 18 V absolute maximum rating provides headroom for transient spikes, confirming robust 15 V operation.
How does the Schmitt-trigger input on the HEF4013BP,652 improve system reliability?
The Schmitt-trigger input on the HEF4013BP,652 provides ~1.5 V hysteresis at 5 V supply, rejecting noise and preventing multiple clock triggers from slow or noisy edges. This eliminates false triggering in applications like mechanical switch debouncing, RC oscillator interfaces, or long PCB traces-ensuring one clean state transition per intended edge. The HEF4013BP,652 thus improves timing determinism without external components.
Is the HEF4013BP,652 pin-compatible with older HEF4013B variants?
Yes, the HEF4013BP,652 is fully pin-compatible with legacy HEF4013B devices in SO14 (SOT108-1) packaging, including identical pin numbering, function mapping, and mechanical footprint. It maintains backward compatibility with existing PCB layouts and schematics while incorporating updated ESD protection and tighter parametric tolerances per Rev. 12 datasheet. No redesign is needed when upgrading to HEF4013BP,652.
HEF4013BP,652 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 4000B
- Package/Case:
- 14-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Function:
- Set(Preset) and Reset
- Type:
- D-Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 40 MHz
- Max Propagation Delay @ V, Max CL:
- 60ns @ 15V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 3.4mA, 3.4mA
- Voltage - Supply:
- 3V ~ 15V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 7.5 pF
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 14-DIP
HEF4013BP,652 FAQ
1.How can I place an order for HEF4013BP,652 through Aetrix?
Please submit a Request for Quotation (RFQ) for HEF4013BP,652 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HEF4013BP,652 reliable?
The price and inventory of HEF4013BP,652 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HEF4013BP,652 is usually 5 days.
3.What payment methods are accepted for HEF4013BP,652?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HEF4013BP,652 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HEF4013BP,652?
HEF4013BP,652 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HEF4013BP,652 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HEF4013BP,652?
For technical support, including HEF4013BP,652 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HEF4013BP,652 requirements.
6.How does Aetrix verify that HEF4013BP,652 is sourced from the original manufacturer or authorized distributors?
All HEF4013BP,652 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HEF4013BP,652 meets industry standards.
7.What is the process for return or replacement of HEF4013BP,652?
All HEF4013BP,652 units undergo pre-shipment inspection (PSI). If there is an issue with HEF4013BP,652, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HEF4013BP,652 part is unused and in its original packaging.
Return procedure for HEF4013BP,652:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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