Nexperia USA Inc. HEF4017BT,652

Overview

HEF4017BT,652 from Nexperia is a CMOS 5-stage Johnson decade counter IC with ten active-HIGH decoded outputs (Q0–Q9), dual-edge-triggered clock inputs (CP0 and CP1), an asynchronous master reset (MR), and an active-LOW carry output (Q5-9). It operates from 3 V to 15 V, supports -40 °C to +125 °C ambient, and delivers spike-free sequential decoding for timing and control circuits in industrial sequencers and LED chasers.

For engineers reviewing the HEF4017BT,652 datasheet, HEF4017BT,652 pinout, HEF4017BT,652 application, or HEF4017BT,652 equivalent, key selection considerations include dual-clock edge sensitivity, automatic illegal-state recovery within 11 clocks, Schmitt-trigger clock inputs for slow-rise tolerance, and SO16 package compatibility with legacy 4000-series layouts.

Technical Context

The HEF4017BT,652 implements a 5-flip-flop Johnson counter architecture that generates a 10-state sequence with overlapping decoded outputs-each output active for one full clock cycle. Its dual-clock interface allows counting on either CP0's LOW-to-HIGH transition (with CP1 LOW) or CP1's HIGH-to-LOW transition (with CP0 HIGH), enabling flexible synchronization across cascaded stages.

Internal automatic code correction resets illegal states within ≤11 clock pulses, ensuring deterministic operation after power-up or glitch events. Schmitt-trigger inputs provide hysteresis (typ. 1.0 V at VDD = 5 V), allowing reliable triggering even with RC-filtered or noisy clock sources up to 30 MHz at 15 V supply.

Key Specifications

Pinout & Package

HEF4017BT,652 is housed in a plastic small outline package (SO16), SOT109-1, with 16 leads, 3.9 mm body width, and standard JEDEC MS-012 footprint compatible with automated PCB assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar decade counter applications.

Compared with CD4017BE and MC14017BCP, the HEF4017BT,652 offers extended temperature range, guaranteed Schmitt-trigger behavior, tighter timing specs, and formal JEDEC compliance-making it the robust choice for new industrial and automotive-adjacent designs where reliability and long-term supply continuity matter.

Availability

HEF4017BT,652 is available at Aetrix Electronics and suitable for industrial timer modules, LED chaser circuits, relay bank sequencers, and stepper motor indexer designs requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for HEF4017BT,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.

The HEF4017BT,652 belongs to Nexperia's 4000B-series CMOS logic family, engineered for robustness in harsh environments and designed to replace legacy CD4000/MC14000 devices while meeting modern reliability and qualification standards.

FAQ

Can HEF4017BT,652 operate reliably at 3.3 V?

Yes - the device is fully characterized down to 3.0 V supply voltage. At 3.3 V, propagation delay increases to ~140 ns (typ.), output drive drops to ~0.8 mA, and Schmitt thresholds scale proportionally. All static and dynamic parameters remain within datasheet limits, making it suitable for mixed-voltage 3.3 V/5 V systems with appropriate level translation on control lines.

How does the Q5-9 carry output function in cascaded configurations?

Q5-9 goes LOW during count states 5 through 9 and HIGH otherwise. When wired to CP0 of a second HEF4017BT,652, it advances the slave counter once per 5–9 sequence - effectively creating a modulo-50 counter. The active-LOW polarity ensures clean edge alignment without additional inverters, and its timing is synchronized to the master's internal state transitions.

What is the minimum pulse width required for the MR input?

The MR input requires a minimum HIGH pulse width of 20 ns at VDD = 15 V, increasing to 60 ns at VDD = 5 V (per Table 7). This ensures reliable asynchronous reset across the full operating voltage and temperature range. For robustness in noisy environments, a 100 ns pulse is recommended, generated by a simple RC differentiator or microcontroller GPIO with configurable pulse width.

Is the HEF4017BT,652 pin-compatible with older CD4017 variants?

Yes - the SO16 pinout matches CD4017BE and MC14017BCP exactly: Q0–Q9, CP0, CP1, MR, VDD, and VSS occupy identical positions. However, due to differences in input hysteresis, timing, and temperature rating, direct substitution is safe only if the application operates within the narrower specs of legacy parts; full validation is advised for new designs targeting -40 °C to +125 °C.