Nexperia USA Inc. HEF4047BT,652

Overview

HEF4047BT,652 from Nexperia is a CMOS retriggerable monostable/astable multivibrator in SO14 package, operating from 3 V to 15 V, with true/complemented buffered outputs (O, O), oscillator output (pin 13), and external RC timing (Rt/Ct) for programmable pulse width or frequency. It supports positive/negative-edge monostable triggering and gateable astable operation, used in timing control, waveform generation, and digital clock conditioning circuits.

For engineers reviewing the HEF4047BT,652 datasheet, HEF4047BT,652 pinout, HEF4047BT,652 application, or HEF4047BT,652 equivalent, key selection considerations include RC-timed pulse width accuracy (±7% at 10 V), retrigger capability, ESD robustness (HBM >2000 V), and compatibility with 5 V/10 V/15 V logic systems requiring stable edge-triggered one-shot or free-running square-wave generation.

Technical Context

The HEF4047BT,652 integrates dual-mode operation: astable mode delivers 50% duty-cycle square waves at O/O (period = 4.40·Rt·Ct) and half-period signal at OSCILLATOR OUTPUT (pin 13); monostable mode provides edge-triggered pulses (t_M = 2.48·Rt·Ct) with retriggering via simultaneous +TRIGGER and RETRIGGER inputs. Its internal flip-flop architecture enables fast recovery independent of pulse width and maintains pulse-width accuracy up to 100% duty cycle.

Input clamping diodes allow interface to voltages beyond V_CC using current-limiting resistors. The RCTC pin (pin 3) features enhanced ESD sensitivity requiring handling precautions. All modes require external Rt between RTC (pin 2) and RCTC (pin 3), and Ct between CTC (pin 1) and RCTC (pin 3).

Key Specifications

Pinout & Package

HEF4047BT,652 uses the SOT108-1 (SO14) plastic small outline package: 14-pin, 3.9 mm body width, 1.27 mm pitch, surface-mount compatible with standard reflow profiles.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multivibrator applications.

Compared with CD4047BE and 74HC4047, the HEF4047BT,652 uniquely balances wide supply range (3–15 V), integrated overvoltage input protection, and retrigger timing fidelity - making it optimal for industrial timing where voltage flexibility and robustness outweigh raw speed.

Availability

HEF4047BT,652 is available at Aetrix Electronics and suitable for industrial automation timing, test equipment clock conditioning, LED driver PWM generation, and HMI debounce circuits requiring stable component supply across extended temperature ranges and mixed-voltage environments.

Supply support for HEF4047BT,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete, logic, and MOSFET solutions for automotive, industrial, and consumer markets.

The HEF4047BT,652 belongs to Nexperia's legacy CMOS logic portfolio designed for robust, low-power timing functions in harsh industrial environments - emphasizing long-term availability, wide voltage operation, and ESD resilience over ultra-high speed.

FAQ

What is the minimum external capacitor value recommended for stable timing operation?

The datasheet specifies Ct ≥ 100 pF for compliance with timing formulae without trimming. Using smaller values increases susceptibility to stray capacitance errors and reduces pulse-width accuracy. Capacitors below 100 pF may cause frequency drift or failure to oscillate reliably, especially at high VDD or elevated temperatures.

Can the HEF4047BT,652 generate a 50% duty cycle at the OSCILLATOR OUTPUT (pin 13)?

No - the OSCILLATOR OUTPUT provides a signal with half the period of O/O outputs, but its duty cycle is not guaranteed to be 50%. Only the O and O outputs deliver a stable 50% duty cycle in astable mode. Pin 13 is intended for frequency doubling or auxiliary clock distribution, not precision duty-cycle applications.

How does the RETRIGGER input interact with the +TRIGGER input in monostable mode?

When both RETRIGGER (pin 12) and +TRIGGER (pin 8) receive coincident rising edges, the output pulse remains HIGH as long as retrigger pulses arrive faster than the RC-set timeout (2.48·Rt·Ct). This extends the effective pulse width incrementally - each new trigger resets the internal timer, enabling dynamic pulse stretching without external logic.

Is the MR (master reset) pin active during power-up, and how should it be handled?

Yes - a HIGH level on MR is required at power-on to prevent spurious output pulses. It must be held HIGH until VDD stabilizes, then driven LOW to enable normal operation. An RC network (e.g., 10 kΩ pull-down + 100 nF to VDD) provides reliable power-on reset, satisfying the requirement for glitch-free initialization per datasheet Section 6.