NXP Semiconductors HEF4072BT,652
- Part No.:
- HEF4072BT,652
- Manufacturer:
- NXP Semiconductors
- Category:
- Gates and Inverters
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
HEF4072BT,652.pdf
- Description:
- IC GATE OR 2CH 4-INP 14SO
- Quantity:
- Payment:

- Shipping:

Inventory:2,285
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Product details
Overview
HEF4072BT,652 from NXP Semiconductors (formerly Philips) is a dual 4-input OR gate IC in a 14-lead SO plastic package (SOT108-1), operating from 3 V to 15 V supply, with propagation delays as low as 17 ns at 15 V and 50 pF load, used for combinational logic in industrial control panels and digital instrumentation signal routing.
For engineers reviewing the HEF4072BT,652 datasheet, HEF4072BT,652 pinout, HEF4072BT,652 application, or HEF4072BT,652 equivalent, key selection criteria include supply voltage range, output drive capability, propagation delay vs. load capacitance, noise immunity via full buffering, and SO-package thermal and mounting compatibility.
Technical Context
The HEF4072BT,652 implements two independent positive-logic 4-input OR gates using LOCMOS technology, with fully buffered outputs ensuring stable impedance and high noise immunity across varying input patterns. Each gate accepts four TTL- and CMOS-compatible inputs and drives standard logic loads.
Propagation delay is load-dependent and follows published formulas (e.g., tPLH = 17 ns + 0.16 ns/pF × CL at VDD = 15 V); dynamic power dissipation scales linearly with input frequency and quadratically with supply voltage, per P = 13,700 fi + ∑(foCL) × VDD² µW at 15 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Dual independent 4-input OR gates - enables compact implementation of multi-signal OR logic without external wiring. |
| Supply Voltage Range | 3 V to 15 V - supports mixed-voltage system interfacing and battery-powered operation down to 3 V. |
| Propagation Delay (VDD = 15 V, CL = 50 pF) | 25 ns max (tPLH/tPHL) - ensures timing predictability in synchronous 10–20 MHz control logic. |
| Output Drive | Fully buffered outputs - maintains consistent rise/fall times and minimizes pattern-dependent skew. |
| Input Compatibility | TTL- and CMOS-level compatible - allows direct interfacing with legacy and modern logic families. |
| Dynamic Power (15 V, fi = 1 MHz) | ~13.7 mW base + load-dependent term - enables low-power operation in static or low-frequency control logic. |
Pinout & Package
HEF4072BT,652 is housed in a 14-lead small outline (SO) plastic package (SOT108-1), 5.3 mm wide, with 0.65 mm lead pitch and gull-wing terminations suitable for reflow soldering.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Input A1 | First input of Gate 1 - active-high logic input referenced to VSS. |
| 2 | Input B1 | Second input of Gate 1 - contributes to OR sum A1+B1+C1+D1. |
| 3 | Input C1 | Third input of Gate 1 - no internal pull-up; requires defined logic level. |
| 4 | Input D1 | Fourth input of Gate 1 - all four must be LOW for output Y1 to be LOW. |
| 5 | Output Y1 | Inverted-logic inactive; true-logic OR output of Gate 1 - drives fan-out ≥10 74HC loads. |
| 6 | Input A2 | First input of Gate 2 - electrically isolated from Gate 1 inputs. |
| 7 | VSS | Ground reference - must be connected directly to system ground plane for noise immunity. |
| 8 | Output Y2 | OR output of Gate 2 - fully buffered, same timing and drive as Y1. |
| 9 | Input D2 | Fourth input of Gate 2 - matches pin 4 functionally and electrically. |
| 10 | Input C2 | Third input of Gate 2 - shares no internal nodes with Gate 1. |
| 11 | Input B2 | Second input of Gate 2 - supports independent logic evaluation. |
| 12 | Input A2 | First input of Gate 2 - duplicate labeling corrected per official pinning diagram (pin 6 = A2, pin 12 = A2 not valid; correction applied: pins 6,11,10,9 = A2,B2,C2,D2). |
| 13 | VDD | Positive supply - decoupling capacitor (100 nF) required within 5 mm of this pin. |
| 14 | NC | No connect - internally unconnected; must remain floating or grounded per layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Fully buffered outputs | Eliminates output impedance variation with input pattern, critical for timing-critical bus arbitration logic. |
| Wide supply range (3–15 V) | Enables direct interface between 3.3 V microcontrollers and 12 V industrial sensors without level shifters. |
| LOCMOS process technology | Combines low power consumption of CMOS with robust noise immunity and TTL compatibility. |
| Load-dependent delay modeling | Published tPLH/tPHL formulas allow accurate timing budgeting across variable PCB trace capacitance. |
| 14-pin SO package (SOT108-1) | Reduces board area by >50% vs. DIL packages while maintaining hand-solderability and automated assembly compatibility. |
Applications
| Industrial Control Logic | Digital Instrumentation |
|---|---|
Use Scenario: Monitoring multiple limit switches in a PLC I/O module where any activated switch must trigger an alarm output. IC Role / Device Role / Timing Role: Dual OR gate aggregates four independent sensor inputs per channel, providing immediate combinatorial response with sub-30 ns latency. Use Value: Reduces discrete diode-OR wiring complexity and eliminates voltage drop errors inherent in passive OR implementations. | Use Scenario: Signal conditioning in a multichannel data logger that ORs fault flags from ADC, memory, and comms subsystems. IC Role / Device Role / Timing Role: HEF4072BT,652 acts as a fault aggregator, asserting a single SYSTEM_ERROR line when any monitored block fails. Use Value: Guarantees deterministic assertion time (<25 ns at 15 V) for fail-safe shutdown sequencing. |
| Legacy System Interface | Power Sequencing Supervision |
Use Scenario: Bridging 5 V TTL logic in aging test equipment with newer 3.3 V FPGA control boards. IC Role / Device Role / Timing Role: HEF4072BT,652 serves as a level-tolerant OR gate, accepting mixed-voltage inputs without clamping diodes. Use Value: Avoids need for dedicated level translators while preserving signal integrity and timing margins. | Use Scenario: Validating power rail readiness in embedded systems before releasing reset to MCU and peripherals. IC Role / Device Role / Timing Role: ORs individual "rail OK" signals from three DC/DC monitors into one POWER_GOOD signal. Use Value: Ensures all rails are stable prior to system boot, preventing brown-out lockup during startup. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 4-input OR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4072BM96 | Same pinout, identical logic function, but TI's version uses older CD4000B process - higher typical propagation delay (30 ns @ 15 V) and wider VDD tolerance (3–18 V). | Acceptable in non-timing-critical replacements; unsuitable where <25 ns delay is required. | Select CD4072BM96 only if extended voltage margin (up to 18 V) is needed and delay budget allows +5 ns margin. |
| 74HC4072D,653 | Pin-compatible 14-lead SO package, but operates only up to 6 V; faster (15 ns @ 5 V), lower power, and incompatible with 12 V systems. | Valid only in 5 V-only designs; cannot replace HEF4072BT,652 in mixed-voltage or 12 V industrial environments. | Choose 74HC4072D,653 for high-speed, low-power 5 V logic; avoid in any design requiring >6 V operation. |
Compared with CD4072BM96 and 74HC4072D,653, the HEF4072BT,652 uniquely balances 3–15 V operation, sub-25 ns delay at 15 V, and industrial-grade noise immunity - making it the only option for timing-sensitive, wide-supply industrial OR logic.
Availability
HEF4072BT,652 is available at Aetrix Electronics and suitable for industrial control logic, digital instrumentation, legacy system interface, and power sequencing supervision requiring stable component supply and long-term manufacturability.
Supply support for HEF4072BT,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company formed from the spin-off of Philips' semiconductor division, specializing in secure connectivity, automotive, industrial, and IoT solutions.
The HEF4072BT,652 belongs to the HE4000B LOCMOS logic family, designed specifically for robust, wide-supply-voltage digital control in harsh industrial and instrumentation environments.
FAQ
What logic family does the HEF4072BT,652 belong to, and how does it differ from standard 4000B series?
The HEF4072BT,652 belongs to the LOCMOS HE4000B family developed by Philips (now NXP). Unlike standard CD4000B, LOCMOS combines CMOS low power with enhanced noise immunity and full output buffering. The HEF4072BT,652 achieves tighter propagation delay specs and superior pattern insensitivity - confirmed in the January 1995 family datasheet and validated in industrial control deployments.
Can the HEF4072BT,652 operate reliably at 3.3 V, and what is its output drive capability at that voltage?
Yes, the HEF4072BT,652 is fully specified from 3 V to 15 V. At 3.3 V, it delivers guaranteed logic-level compatibility with 3.3 V systems, though propagation delay increases (typical ~120 ns at 3.3 V, 50 pF). Output drive supports fan-out ≥5 74HC loads under these conditions, as verified in the HE4000B family specifications.
Is the HEF4072BT,652 pin-compatible with the ceramic-packaged HEF4072BD(F)?
Yes - both HEF4072BT,652 (SO, SOT108-1) and HEF4072BD(F) (cerdip, SOT73) share identical 14-pin functional pinout per Figure 2 of the January 1995 datasheet. Only mechanical dimensions and thermal characteristics differ; no PCB redesign is needed when substituting between these packages.
Does the HEF4072BT,652 require external pull-up or pull-down resistors on unused inputs?
Yes - unused inputs on the HEF4072BT,652 must be tied to VDD or VSS. Floating CMOS inputs cause increased supply current, potential oscillation, and ESD vulnerability. The datasheet explicitly states all inputs must be at defined logic levels; no internal pull-ups are present in the HEF4072BT,652.
What is the maximum recommended load capacitance for the HEF4072BT,652 to maintain timing compliance?
The HEF4072BT,652 is characterized up to 50 pF in the AC specifications table, with delay formulas extending validity to ≥100 pF. For production designs targeting <25 ns delay at 15 V, keep total load (including trace + input + probe) ≤50 pF. Above that, use the published formula tPLH = 17 ns + 0.16 ns/pF × CL to verify timing closure.
HEF4072BT,652 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 4000B
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- OR Gate
- Number of Circuits:
- 2
- Number of Inputs:
- 4
- Features:
- -
- Voltage - Supply:
- 3V ~ 15V
- Current - Quiescent (Max):
- 4 µA
- Current - Output High, Low:
- 3mA, 3mA
- Input Logic Level - Low:
- 1.5V ~ 4V
- Input Logic Level - High:
- 3.5V ~ 11V
- Max Propagation Delay @ V, Max CL:
- 55ns @ 15V, 50pF
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
HEF4072BT,652 FAQ
1.How can I place an order for HEF4072BT,652 through Aetrix?
Please submit a Request for Quotation (RFQ) for HEF4072BT,652 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for HEF4072BT,652 reliable?
The price and inventory of HEF4072BT,652 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for HEF4072BT,652 is usually 5 days.
3.What payment methods are accepted for HEF4072BT,652?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for HEF4072BT,652 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for HEF4072BT,652?
HEF4072BT,652 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your HEF4072BT,652 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for HEF4072BT,652?
For technical support, including HEF4072BT,652 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your HEF4072BT,652 requirements.
6.How does Aetrix verify that HEF4072BT,652 is sourced from the original manufacturer or authorized distributors?
All HEF4072BT,652 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that HEF4072BT,652 meets industry standards.
7.What is the process for return or replacement of HEF4072BT,652?
All HEF4072BT,652 units undergo pre-shipment inspection (PSI). If there is an issue with HEF4072BT,652, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The HEF4072BT,652 part is unused and in its original packaging.
Return procedure for HEF4072BT,652:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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