Nexperia USA Inc. HEF4094BT,652

Overview

HEF4094BT,652 from Nexperia is an 8-bit CMOS serial-in/parallel-out shift-and-store register with independent shift and storage registers, 3-state outputs, dual serial outputs (QS1/QS2) for cascading, and operation across 3.0 V to 15.0 V supply. It features separate CP and STR clocks, OE-controlled high-impedance outputs, and is qualified for -40 °C to +125 °C ambient operation - used in remote control holding registers and serial-to-parallel data conversion circuits.

For engineers reviewing the HEF4094BT,652 datasheet, HEF4094BT,652 pinout, HEF4094BT,652 application, or HEF4094BT,652 equivalent, key selection considerations include its dual-edge-cascadable serial outputs (QS1 on CP↑, QS2 on CP↓), 3-state output enable timing (tPZH/tPLZ ≤ 40 ns at 15 V), wide VDD range (3–15 V), and SO16 package compatibility with legacy 4000-series logic designs.

Technical Context

The HEF4094BT,652 implements a two-stage pipeline: an 8-bit shift register accepting serial data on CP rising edges, and a parallel-access storage register loaded synchronously on STR HIGH. Its dual serial outputs provide deterministic latency alignment - QS1 delivers shifted data on the same CP↑ edge, while QS2 provides it on the subsequent CP↓ edge, enabling robust daisy-chaining under varying clock edge rates.

Output control is fully decoupled from register state: OE asserts high-impedance without altering QP0–QP7 or internal register contents. Input clamp diodes allow safe interfacing to voltages exceeding VDD when used with current-limiting resistors - a design feature critical for mixed-voltage system integration and noise-immune signal routing.

Key Specifications

Pinout & Package

HEF4094BT,652 is supplied in the SOT109-1 plastic small outline package (SO16), 16-pin, 3.9 mm body width, with standard 1.27 mm lead pitch and pin 1 index marker.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 8-bit shift-and-store register applications.

Compared with CD4094BE and 74HC595PW, the HEF4094BT,652 uniquely balances wide supply range (3–15 V), dual-cascade outputs for timing margin, and industrial temperature rating - making it optimal for ruggedized, mixed-voltage, or legacy-compatible designs where reliability trumps raw speed.

Availability

HEF4094BT,652 is available at Aetrix Electronics and suitable for remote control interfaces, LED display drivers, industrial I/O expanders, and legacy bus adapters requiring stable component supply across extended temperature and voltage ranges.

Supply support for HEF4094BT,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies - delivering high-performance, reliable, and scalable logic, power, and analog components.

The HEF4094BT,652 belongs to Nexperia's legacy-compatible 4000B logic family, engineered for industrial control, instrumentation, and long-lifecycle equipment where wide voltage operation, ESD robustness, and temperature resilience are mandatory.

FAQ

What is the maximum clock frequency supported by HEF4094BT,652?

The HEF4094BT,652 supports up to 28 MHz at VDD = 15 V, 22 MHz at 10 V, and 10 MHz at 5 V - specified in Table 7 under fmax. These values assume CL ≤ 50 pF and are derived from propagation delay limits (e.g., CP to QPn ≤ 110 ns at 15 V). Real-world frequency is load-dependent and must account for setup/hold times (tsu = 5 ns, th = 5 ns min at 15 V).

Can HEF4094BT,652 drive LEDs directly?

Yes - at VDD = 15 V, each QPn output delivers ≥ 2.4 mA sink current (IOL) and ≥ −2.4 mA source current (IOH), sufficient to drive standard 2 mA LEDs with appropriate current-limiting resistors. Output voltage compliance remains within spec (VOL ≤ 0.05 V, VOH ≥ 14.95 V) under this load, ensuring reliable on/off states without external drivers.

How does QS1 differ from QS2 in cascade configuration?

QS1 outputs the stage-6 value on the same CP rising edge that shifts data into the register, enabling immediate downstream capture with minimal latency. QS2 outputs the stage-7 value on the subsequent CP falling edge - adding one half-cycle delay but improving timing margin in systems with slow or asymmetric clock edges, preventing race conditions in long daisy chains.

Is HEF4094BT,652 pin-compatible with older HEF4094B variants?

Yes - HEF4094BT,652 uses the SOT109-1 (SO16) package identical to the original HEF4094B in SO16, with identical pinout, electrical characteristics, and timing behavior. It maintains full backward compatibility with legacy PCB layouts and firmware, including identical STR, CP, D, OE, and QPn assignments per Figure 4 and Table 2.