NXP Semiconductors HEF4104BP,652

Overview

HEF4104BP,652 from Nexperia is a quad low-to-high voltage translator IC with complementary 3-state outputs (Bn and Bn), designed for bidirectional level shifting between two independent supply domains (VDD(A) and VDD(B)). It supports 5 V/10 V/15 V parametric ratings, operates from -40 °C to +85 °C, and features input clamp diodes enabling safe interfacing to voltages exceeding VDD(A). It is used in mixed-voltage digital systems such as industrial PLC I/O modules.

For engineers reviewing the HEF4104BP,652 datasheet, HEF4104BP,652 pinout, HEF4104BP,652 application, or HEF4104BP,652 equivalent, key selection considerations include dual-supply voltage translation capability, 3-state output control via OE, JEDEC JESD13-B compliance, HBM ESD rating >2000 V, and SO16 package compatibility with legacy 4000-series logic footprints.

Technical Context

The HEF4104BP,652 implements four independent CMOS-based level-conversion channels, each accepting inputs referenced to VDD(A) and driving complementary outputs referenced to VDD(B). Its functional diagram shows discrete level-converter blocks per channel, with shared OE control enabling simultaneous high-impedance disable of all eight outputs (B0–B3 and B0–B3).

Operation requires VDD(B) ≥ VDD(A) (per Fig. 4), supporting translation from lower-voltage logic (e.g., 3.3 V or 5 V microcontrollers) to higher-voltage interfaces (e.g., 10 V or 15 V industrial sensors or actuators). Input clamping diodes allow current-limited overvoltage tolerance up to VDD(A)+0.5 V, and static operation ensures stable DC-level translation without timing constraints.

Key Specifications

Pinout & Package

HEF4104BP,652 is housed in a plastic small outline package (SO16) per SOT109-1 standard: 16-pin, 3.9 mm body width, 1.27 mm lead pitch, with pin 1 index marking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage translation applications.

Compared with SN74LVC4245APWR and TXS0108E, the HEF4104BP,652 uniquely delivers complementary true/inverted outputs per channel, supports up to 15 V VDD(B), and retains explicit OE control-making it irreplaceable in applications requiring simultaneous active-HIGH and active-LOW signaling at elevated voltages.

Availability

HEF4104BP,652 is available at Aetrix Electronics and suitable for industrial sensor interfaces, legacy system upgrades, and programmable logic I/O expansion requiring stable component supply across extended temperature ranges.

Supply support for HEF4104BP,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, reliable standard logic, analog, and discrete components for industrial, automotive, and computing markets.

The HEF4104BP,652 belongs to Nexperia's HEF4000B logic family, engineered for robust mixed-voltage system interfacing with emphasis on industrial reliability, wide supply flexibility, and JEDEC-compliant interoperability.

FAQ

What is the maximum allowable voltage difference between VDD(A) and VDD(B) for HEF4104BP,652?

The HEF4104BP,652 requires VDD(B) ≥ VDD(A), with absolute maximum ratings of -0.5 V to +18 V for each supply. The permissible operating area (Fig. 4) confirms that VDD(B) must be equal to or greater than VDD(A), but no fixed maximum delta-V is specified-designs must ensure VDD(B) remains within its 18 V absolute max while satisfying VDD(B) ≥ VDD(A). For example, VDD(A) = 5 V and VDD(B) = 15 V is valid; VDD(A) = 10 V and VDD(B) = 10 V is also valid.

Can HEF4104BP,652 translate signals from 3.3 V logic to 12 V outputs?

Yes, HEF4104BP,652 supports translation from 3.3 V inputs (within its 3.0 V–15.0 V VDD(A) range) to 12 V outputs (within its VDD(B) range up to 15 V). Input voltage thresholds scale with VDD(A): VIH is ≥11.0 V at VDD(A)=15 V, but at VDD(A)=3.3 V, VIH is ≥2.3 V (extrapolated from Table 6 min/max ratios). Thus, standard 3.3 V CMOS outputs meet the VIH requirement when VDD(A)=3.3 V, and outputs swing fully to 12 V when VDD(B)=12 V.

Does HEF4104BP,652 require external pull-up resistors on its Bn/Bn outputs?

No, HEF4104BP,652 does not require external pull-up resistors on Bn or Bn outputs because it features active push-pull CMOS outputs capable of sourcing and sinking current (±3.6 mA at 15 V). Pull-ups are unnecessary unless open-drain emulation is needed-but the device's native 3-state and complementary output architecture makes external resistors redundant for standard logic interfacing.

How does the OE pin affect the complementary outputs Bn and Bn in HEF4104BP,652?

When OE is LOW, both Bn and Bn outputs per channel enter high-impedance (Z) simultaneously, regardless of input state-this is confirmed in Table 3. When OE is HIGH, Bn follows An and Bn is its logical inverse. This synchronized 3-state control allows clean bus isolation in multi-device systems, preventing contention during reset or standby modes in the HEF4104BP,652.

Is HEF4104BP,652 pin-compatible with older HEF4104B variants like HEF4104BT?

Yes, HEF4104BP,652 shares the identical SOT109-1 (SO16) pinout and electrical specifications with HEF4104BT and other HEF4104B variants per Nexperia's ordering information (Table 1) and pinning diagrams (Fig. 3). The "P" suffix denotes the plastic DIP package in historical variants, but HEF4104BP,652 is the SO16 version-confirmed by package description "SO16" and version "SOT109-1" in the datasheet, making it mechanically and electrically interchangeable with HEF4104BT in SO16 footprint designs.